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| 型号： | TSB43AA82PGE |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 89/146页 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
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321
BITS
DESCRIPTION
DIR
ACRONYM
22
ARRtry
R/O
Autoresponse retry. When the autoresponse transaction begins retrying because of a received
ack_busy_X, ARRtry is set to 1. When the autoresponse retry transaction ends because an
acknowledgement other than ack_busy_X, a retry time-out, or a bus reset was received, ARRtry is set to 0.
This bit defaults to 0 and is set to 0 on a bus reset.
23
Reserved
N/A
Reserved
2427
TimrNo
R/W
Transaction timer number. The host writes to TimrNo to indicate which timer to control and status. The
timer selected by TimrNo determines the FIFO timer controlled by TxAbrt and HldRtr, and the status read
from transaction timer status1-3 (64h6Ch). This field defaults to 0 and is set to 0 on a bus reset.
0h : The timer of transmission from DTF
1h : The timer of transmission from DRF
2h : The timer of transmission from ATF
3h : The timer of transmission from MTQ
4h : The timer of transmission from CTQ
5h : Reserved
6h : The timer of autoresponse(AR) transmission
7h : Reserved
28
TxAbrt
S/C
Transaction abort. When TxAbrt is set to 1, the transaction of the timer indicated in TimrNo is aborted.
TxAbrt clears itself after the abort. This bit defaults to 0 and is set to 0 on a bus reset.
Note: DTErr (60h) is set to 1 when the DTF transaction is aborted.
29
HldTr
S/C
Hold transmission. When HldTr is set to 1, the transmission of the timer indicated in TimerNo is suspended.
If both HldTr and RlsTr are set to 1 at the same time, HldTr is ignored and the transaction is aborted. This bit
defaults to 0 and is set to 0 on a bus reset.
Note: It is necessary to set this bit to 1 when writing to the ATF, the MTQ, and the CTQ. Then transmit
packet by setting RlsTr to 1.
30
RlsTr
S/C
Release transmission. When RlsTr is set to 1, the suspended transmission of the timer indicated by
TimerNo is released/restarted. RlsTr clears itself after the transmission is released. This bit defaults to 0
and is set to 0 on a bus reset.
31
Reserved
N/A
Reserved
3.4.25 Transaction Timer Status Registers at 64h, 68h, 6Ch
These registers default to 0000 0000h and are set to 0000 0000h on a bus reset. These registers are the status
registers of the timer selected by TimrNo at 60h.
3.4.25.1 Transaction Timer Status Register 1 at 64h
BITS
ACRONYM
DIR
DESCRIPTION
015
Destination_ID
R/O
TimerNo’s transmitting destination ID. The timer defined by TimrNo at 60h is transmitting or has
transmitted the request packet to the destination ID in the last transaction.
1631
Destination_offset_hi
R/O
TimerNo’s transmitting destination offset high. The timer defined by TimrNo at 60h is transmitting or has
transmitted the request packet to Destination_offset_hi in the last transaction.
3.4.25.2 Transaction Timer Status Register 2 at 68h
BITS
ACRONYM
DIR
DESCRIPTION
031
Destination_offset_lo
R/O
TimerNo’s transmitting destination offset low. The timer defined by TimrNo at 60h is transmitting or has
transmitted the request packet to Destination_offset_lo in the last transaction.
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