参数资料
型号: UDA1342TSDB-T
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: Audio CODEC
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封装: 5.30 MM, ROHS COMPLIANT, PLASTIC, MO-150, SSOP-28
文件页数: 27/48页
文件大小: 304K
代理商: UDA1342TSDB-T
2000 Jul 31
33
Philips Semiconductors
Product specication
Audio CODEC
UDA1342TS
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency.
2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
small as possible.
3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1
64fs cycle.
4. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
5. After this period, the first clock pulse is generated.
6. To be suppressed by the input filter.
tstp(L3)
L3MODE stop time in data
transfer mode
190
ns
tsu(L3)DA
L3DATA set-up time in address
and data transfer mode
190
ns
th(L3)DA
L3DATA hold time in address and
data transfer mode
30
ns
tsu(L3)R
L3DATA set-up time for read data
50
ns
th(L3)R
L3DATA hold time for read data
360
ns
ten(L3)R
L3DATA enable time for read data
380
ns
tdis(L3)R
L3DATA disable time for read data
50
ns
I2C-bus interface timing (see Fig.15)
fSCL
SCL clock frequency
0
400
kHz
tLOW
SCL LOW time
1.3
s
tHIGH
SCL HIGH time
0.6
s
tr
rise time SDA and SCL
note 4
20 + 0.1Cb
300
ns
tf
fall time SDA and SCL
note 4
20 + 0.1Cb
300
ns
tHD;STA
hold time START condition
note 5
0.6
s
tSU;STA
set-up time repeated START
0.6
s
tSU;STO
set-up time STOP condition
0.6
s
tBUF
bus free time between a STOP
and START condition
1.3
s
tSU;DAT
data set-up time
100
ns
tHD;DAT
data hold time
0
s
tSP
pulse width of spikes
note 6
0
50
ns
Cb
capacitive load for each bus line
400
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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