参数资料
型号: UDA1342TSDB-T
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: Audio CODEC
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封装: 5.30 MM, ROHS COMPLIANT, PLASTIC, MO-150, SSOP-28
文件页数: 8/48页
文件大小: 304K
代理商: UDA1342TSDB-T
2000 Jul 31
16
Philips Semiconductors
Product specication
Audio CODEC
UDA1342TS
8.15.4
DATA WRITE MODE
The data write format is given in Table 13 and illustrated
in Fig.9.
When writing data to a device four bytes must be sent:
1. One byte with the device address, being ‘01X0 1000’
where ‘X’ stands for the IPSEL value, including ‘01’ for
signalling write to the device.
2. One byte starting with a logic 0 for signalling write
followed by 7 bits indicating the register address.
3. One byte which is the Most Significant Data (MSD)
byte 1.
4. One byte which is the Least Significant Data (LSD)
byte 2.
8.15.5
DATA READ MODE
The data write format is given in Table 14 and illustrated
in Fig.10.
When reading from the device, a prepare read must first be
done. After the prepare read, the device address is sent
again. The device then returns with the register address,
indicating whether the address was valid or not, and the
data of the register.
The data read mode is explained below:
1. One byte with the device address, being ‘01X0 1000’
where ‘X’ stands for the IPSEL value, including ‘01’ for
signalling write to the device.
2. One byte is sent with the register address which needs
to be read. This byte starts with a logic 1, which
indicates that there will be a read action from the
register.
3. One byte with the device address including ‘11’ is sent
to the device. The ‘11’ indicates that the device must
write data to the microcontroller.
4. The device now writes the requested register address
on the L3-bus, indicating whether the requested
register was valid (logic 0) or invalid (logic 1).
5. The device writes data from the requested register to
the L3-bus with the MSD byte 1 first, followed by the
LSD byte 2.
Table 13 L3-bus format for data write
Table 14 L3-bus format for prepare read and read data
L3MODE
DATA TYPE
FIRST IN TIME
LAST IN TIME
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Address
device address
0
1
IPSEL
01000
Data transfer 1
register address
0
A6
A5
A4
A3
A2
A1
A0
Data transfer 2
MSD byte 1
D15
D14
D13
D12
D11
D10
D9
D8
Data transfer 3
LSD byte 2
D7
D6
D5
D4
D3
D2
D1
D0
L3MODE
DATA TYPE
FIRST IN TIME
LAST IN TIME
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Prepare read
Address
device address
0
1
IPSEL
01000
Data transfer 1
register address
1
A6
A5
A4
A3
A2
A1
A0
Read data
Address
device address
1
IPSEL
01000
Data transfer 1
register address
0/1
A6
A5
A4
A3
A2
A1
A0
Data transfer 2
MSD byte 1
D15
D14
D13
D12
D11
D10
D9
D8
Data transfer 3
LSD byte 2
D7
D6
D5
D4
D3
D2
D1
D0
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