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参数资料
| 型号： | UDA1342TSDB-T |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Audio CODEC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封装： | 5.30 MM, ROHS COMPLIANT, PLASTIC, MO-150, SSOP-28 |
| 文件页数： | 4/48页 |
| 文件大小： | 304K |
| 代理商： | UDA1342TSDB-T |
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2000 Jul 31
12
Philips Semiconductors
Product specication
Audio CODEC
UDA1342TS
8.11
Sampling speed
The UDA1342TS operates with sample frequencies from
16 to 110 kHz. This range holds for the CODEC as a
whole. The DAC part can be configured in the L3-bus and
I2C-bus mode to accept 2 times and even 4 times the data
speed (e.g. fs is 96 or 192 kHz), but in these modes not all
of the features can be used.
Some examples of the input oversampling rate settings
are shown in Table 4.
Important: in the double speed mode an input signal of
0 dB is allowed, but in the quad speed mode the input
signal must be limited to
6 dB to prevent the system from
clipping.
Table 4
Examples of the input oversampling rate settings
SYSTEM CLOCK
SYSTEM
CLOCK
FREQUENCY
SETTING
SAMPLING
FREQUENCY
(kHz)
INPUT OVER-
SAMPLING
RATE
FEATURES SUPPORTED
12.288 MHz (256
× 48 kHz)
256fs
48
single speed
all
96
double speed
only master volume and mute
192
quad speed
no features
22.5792 MHz (512
× 44.1 kHz)
512fs
44.1
single speed
all
256fs
88.2
single speed
all
176.4
double speed
only master volume and mute
33.8688 MHz (768
× 44.1 kHz)
768fs
44.1
single speed
all
384fs
88.2
single speed
all
176.4
double speed
only master volume and mute
8.12
Power-on reset
The UDA1342TS has an internal Power-on reset circuit
(see Fig.7) which resets the test control block. All the
digital sound processing features and the system
controlling features are set to their default setting in the
L3-bus and I2C-bus mode.
The reset time (see Fig.8) is determined by an external
capacitor which is connected between pin Vref and ground.
The reset time should be at least 1
s for Vref < 1.25 V.
When VDDA(DAC) is switched off, the device will be reset
again for Vref < 0.75 V.
During the reset time the system clock should be running.
handbook, halfpage VDDA(DAC)
Vref
3.0 V
25
28
MGU001
UDA1342TS
C1
>
10
F
RESET
CIRCUIT
8 k
8 k
Fig.7 Power-on reset circuit.
相关PDF资料 |
PDF描述 |
|---|---|
| UDA1342TS/N1,512 | Audio CODEC; Package: SOT341-1 (SSOP28); Container: Tube Dry Pack |
| UDA1342TS/N1,518 | Audio CODEC; Package: SOT341-1 (SSOP28); Container: Reel Dry Pack, SMD, 13" |
| UDA1345TS/N2,118 | Economy audio CODEC; Package: SOT341-1 (SSOP28); Container: Reel Pack, SMD, 13" |
| UDA1345TS/N2,112 | Economy audio CODEC; Package: SOT341-1 (SSOP28); Container: Tube |
| UDA1361TS/N1,112 | 96 kHz sampling 24-bit stereo audio ADC; Package: SOT369-1 (SSOP16); Container: Tube |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UDA1343 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Economy audio CODEC with features |
| UDA1343TT | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Economy audio CODEC with features |
| UDA1344 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Low-voltage low-power stereo audio CODEC with DSP features |
| UDA1344TS | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Low-voltage low-power stereo audio CODEC with DSP features |
| UDA1344TS/N2 | 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO W/DSP 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, W/DSP, 28-SSOP |
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