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参数资料
| 型号： | UDA1342TSDB-T |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Audio CODEC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封装： | 5.30 MM, ROHS COMPLIANT, PLASTIC, MO-150, SSOP-28 |
| 文件页数： | 47/48页 |
| 文件大小： | 304K |
| 代理商： | UDA1342TSDB-T |
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2000 Jul 31
8
Philips Semiconductors
Product specication
Audio CODEC
UDA1342TS
8
FUNCTIONAL DESCRIPTION
8.1
System clock
The UDA1342TS operates in slave mode only, this means
that in all applications the system must provide the system
clock. The system clock frequency is selectable and
depends on the mode of operation:
L3-bus/I2C-bus mode: 256fs, 384fs, 512fs or 768fs
Static pin mode: 256fs or 384fs.
The system clock must be locked in frequency to the digital
interface signals.
Remarks:
The bit clock frequency fBCK can be up to 128fs, or in
other words the bit clock frequency is 128 times the
word select frequency fWS or less: fBCK ≤ 128fWS
The WS edge MUST fall on the negative edge of the
BCK signal at all times for proper operation of the digital
interface
The UDA1342TS operates with sample frequencies
from 16 to 110 kHz, however for a system clock of 768fs
the sampling frequency must be limited to 55 kHz.
8.2
ADC analog front-end
The analog front-end of the UDA1342TS consists of two
stereo ADCs with a programmable gain stage (gain from
0 to 24 dB with 3 dB steps) which can be controlled via the
L3-bus/I2C-bus interface.
8.2.1
APPLICATION WITH 2 V (RMS) INPUT
In applications in which a 2 V (RMS) input signal is used,
a15 k
resistor must be used in series with the input of the
ADC (see Fig.3). This forms a voltage divider together with
the internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC. Using this application for a
2 V (RMS) input signal, the gain switch must be set to
0 dB. When a 1 V (RMS) input signal is input to the ADC in
the same application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1.
Table 1
Application modes using input gain stage
handbook, halfpage
VSSA(ADC)
VINL1
VDDA(ADC)
VINR1
VADCN
VINL2
VADCP
VINR2
IPSEL
VDDD
VSSD
SYSCLK
L3MODE
L3CLOCK
Vref
VSSA(DAC)
VOUTL
VDDA(DAC)
QMUTE
STATUS
VOUTR
STATIC
TEST1
DATAI
DATAO
WS
BCK
L3DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
UDA1342TS
MGT017
Fig.2 Pin configuration.
RESISTOR
(15 k
)
PGA GAIN
MAXIMUM INPUT
VOLTAGE
Present
0 dB
2 V (RMS)
Present
6 dB
1 V (RMS)
Absent
0 dB
1 V (RMS)
Absent
6 dB
0.5 V (RMS)
handbook, halfpage
MGT018
Vref
VINL1,
VINR1,
VINL2,
VINR2
2,
4,
6,
8
gain = 0 dB
10 k
10 k
15 k
input signal
2 V (RMS)
UDA1342TS
Fig.3 Schematic of ADC front-end.
相关PDF资料 |
PDF描述 |
|---|---|
| UDA1342TS/N1,512 | Audio CODEC; Package: SOT341-1 (SSOP28); Container: Tube Dry Pack |
| UDA1342TS/N1,518 | Audio CODEC; Package: SOT341-1 (SSOP28); Container: Reel Dry Pack, SMD, 13" |
| UDA1345TS/N2,118 | Economy audio CODEC; Package: SOT341-1 (SSOP28); Container: Reel Pack, SMD, 13" |
| UDA1345TS/N2,112 | Economy audio CODEC; Package: SOT341-1 (SSOP28); Container: Tube |
| UDA1361TS/N1,112 | 96 kHz sampling 24-bit stereo audio ADC; Package: SOT369-1 (SSOP16); Container: Tube |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UDA1343 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Economy audio CODEC with features |
| UDA1343TT | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Economy audio CODEC with features |
| UDA1344 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Low-voltage low-power stereo audio CODEC with DSP features |
| UDA1344TS | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Low-voltage low-power stereo audio CODEC with DSP features |
| UDA1344TS/N2 | 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO W/DSP 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, W/DSP, 28-SSOP |
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