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CHAPTER 20
FREQUENCY COUNTER
User’s Manual U12790EJ2V0UD
20.3 Registers Controlling Frequency Counter
The frequency counter is controlled by the following three registers.
IF counter mode select register (IFCMD)
IF counter control register (IFCCR)
IF counter gate judge register (IFCJG)
(1) IF counter mode select register (IFCMD)
This register selects the input pin of the frequency counter, and selects the mode and gate time (count time).
This register is set by a 1-bit or 8-bit memory manipulation instruction.
The value of this register is reset to 00H after reset or in the STOP mode.
In the HALT mode, this register holds the value immediately before the HALT mode was set.
Figure 20-2. Format of IF Counter Mode Select Register (IFCMD)
IFCMD1 IFCMD0
Selection of frequency counter pin and mode
0
FMIFC AMIFC pins disabledNote 1
0
1
AMIFC pin, AMIF count modeNote 2
1
0
FMIFC pin, FMIF count modeNote 2
1
FMIFC pin, AMIF count modeNote 2
IFCCK1 IFCCK0
Selection of gate time
0
1 ms
0
1
4 ms
1
0
8 ms
1
Open
Notes 1. The FMIFC and AMFIC pins are used as port pins.
2. When using the AMIFC/P101 and FMIFC/P102 pins to input signals to the frequency counter, set
PM101 and PM102 to 1.
Caution
Any pin not selected by IFCMD is automatically set in the port mode.
Remark
Bits 4 to 7 are fixed to 0 by hardware.
7
0
6
0
5
0
4
0
IFCMD1 IFCMD0 IFCCK1 IFCCK0
Symbol
IFCMD
R/W
After reset
00H
Address
FFA9H
<0>
<1>
<2>
<3>