
558
User’s Manual U12790EJ2V0UD
APPENDIX C
REVISION HISTORY
The revision history of this edition is listed in the table below. “Chapter” indicates the chapter of the previous edition
where the revision was made.
(1/2)
Edition
Revision
Chapter
2nd
Addition of
PD178096A and 178098A
Throughout
Modification of
PD178F098 from under development to developed
Modification of 1.5 Development of 8-Bit DTS Series
CHAPTER 1 OUTLINE
Modification of pin handing in 2.2.26 VPP (
PD178F098 only)
CHAPTER 2 PIN
Modification of Table 2-1 Pin I/O Circuit Types and Figure 2-1 Pin I/O Circuits
FUNCTIONS
Addition of description of programming area in 3.1.2 Internal data memory space
CHAPTER 3 CPU
Modification of Figure 3-10 Data to Be Saved to Stack Memory and
ARCHITECTURE
Figure 3-11 Data to Be Restored from Stack Memory
Modification of [Example] in 3.4.4 Short direct addressing
Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed
addressing, and 3.4.9 Stack addressing
Addition of description of output latches after reset to 4.4 Port Function
CHAPTER 4 PORT
Operations
FUNCTIONS
6.2 Configuration of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT
Addition of Cautions to (2) 16-bit capture/compare register 00 (CR00)
TIMER/EVENT
Addition of Table 6-3 CR01 Capture Trigger and Valid Edge of TI00 Pin
COUNTER 0
(CRC02 = 1)
Addition of Caution to (3) 16-bit capture/compare register 01 (CR01)
Addition of Caution to Figure 6-5 Format of Prescaler Mode Register 0 (PRM0)
6.4.5 One-shot pulse output operation
Modification of Figure 6-26 Timing of One-Shot Pulse Output Operation with
Software Trigger
Addition of Note to (2) One-shot pulse output with external trigger
Addition of 6.5 Program List
Addition of (6) (c) One-shot pulse output function to 6.6 Notes on 16-Bit
Timer/Event Counter 0
7.2 Configuration of 8-Bit Timer/Event Counters 50, 51
CHAPTER 7 8-BIT
Addition of Note to (1) 8-bit timer counters 50 and 51 (TM50 and TM51)
TIMER/EVENT
Addition of description of PWM mode to (2) 8-bit compare registers 50 and 51
COUNTERS
(CR50 and CR51)
Addition of 7.5 Program List
Addition of (4) Noise countermeasures and (6) Input impedance of ANI0 to ANI7 CHAPTER 11 A/D
pins to 11.5 A/D Converter Cautions
CONVERTER
Addition of Figure 16-2 Block Diagram of Baud Rate Generator
CHAPTER 16 SERIAL
Addition of Caution to Figure 16-6 Permissible Error of Baud Rate Allowing
INTERFACE UART0
for Sampling Error (k = 0)
(
PD178076, 178078,
178F098 ONLY)