参数资料
型号: uPSD3212
厂商: 意法半导体
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可编程系统器件)
中文描述: 闪存可编程系统器件与8032微控制器内核(嵌入高速“8032微控制器核”的闪存型可编程系统器件)
文件页数: 37/155页
文件大小: 1055K
代理商: UPSD3212
37/155
μPSD321X
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows.
I
INT0 external interrupt
I
2nd USART interrupt
I
Timer0 interrupt
I
I
2
C interrupt
I
INT1 external interrupt (or ADC interrupt)
I
Timer1 interrupt
I
USART interrupt
I
Timer2 interrupt
External Int0
I
The INT0 can be either level-active or transition-
active depending on Bit IT0 in register TCON.
The flag that actually generates this interrupt is
Bit IE0 in TCON.
I
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
I
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
Timer 0 and 1 Interrupts
I
Timer0 and Timer1 interrupts are generated by
TF0 and TF1 which are set by an overflow of
their respective Timer/Counter registers (except
for Timer0 in Mode 3).
I
These flags are cleared by the internal
hardware when the interrupt is serviced.
Timer 2 Interrupt
I
Timer2 interrupt is generated by TF2 which is
set by an overflow of Timer2. This flag has to be
cleared by the software - not by hardware.
I
It is also generated by the T2EX signal (timer 2
external interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.
I
2
C Interrupt
I
The interrupt of the I
2
C is generated by Bit INTR
in the register S2STA.
I
This flag is cleared by hardware.
External Int1
I
The INT1 can be either level active or transition
active depending on Bit IT1 in register TCON.
The flag that actually generates this interrupt is
Bit IE1 in TCON.
I
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
I
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
I
The ADC can take over the External INT1 to
generate an interrupt on conversion being
completed
相关PDF资料
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相关代理商/技术参数
参数描述
UPSD3212A 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212A-24T6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212A-24U6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212A-40T6 功能描述:8位微控制器 -MCU Flash Programmable System Devices RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
UPSD3212A-40T6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic