参数资料
型号: uPSD3212
厂商: 意法半导体
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可编程系统器件)
中文描述: 闪存可编程系统器件与8032微控制器内核(嵌入高速“8032微控制器核”的闪存型可编程系统器件)
文件页数: 95/155页
文件大小: 1055K
代理商: UPSD3212
95/155
μPSD321X
Reset Flash.
The Reset Flash instruction con-
sists of one WRITE cycle (see Table 62). It can
also be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device
has set the Error Flag Bit (DQ5) to '1' during a
Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memo-
ry back into normal READ Mode. If an Error condi-
tion has occurred (and the device has set the Error
Flag Bit (DQ5) to '1' the Flash memory is put back
into normal READ Mode within a few milliseconds
of the Reset Flash instruction having been issued.
The Reset Flash instruction is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within a
few milliseconds .
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (V
STBY
, PC2). If you have an
external battery connected to the μPSD3200, the
contents of the SRAM are retained in the event of
a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (V
BATON
, PC4) is High
with the supply voltage falls below the battery volt-
age and the battery on Voltage Stand-by (V
STBY
,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (V
STBY
,
PC2) and Battery-on Indicator (V
BATON
, PC4) are
all configured using PSDsoft Express Configura-
tion.
Sector Select and SRAM Select
Sector Select (FS0-FS3, CSBOOT0-CSBOOT1)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDsoft Express. The following rules ap-
ply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must notbe larg-
er than the physical sector size.
2. Any primary Flash memory sector must not be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must not be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must not
overlap.
5. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
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