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参数资料
| 型号： | V59C1G01164QAUF37H |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, PBGA92 |
| 封装： | ROHS COMPLIANT, FBGA-92 |
| 文件页数： | 36/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1G01164QAUF37H |
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41
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Burst Write followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a
delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be
issued. This delay is known as a write recovery time (t WR ) referenced from the completion of the burst write
to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2
SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter
(see the AC table in this datasheet) and is not the programmed value for tWR in the MRS.
Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3
Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3
NOP
WRITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
WL = 3
BW-P3
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tWR
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK
NOP
WRITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = 4
BW-P4
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tWR
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK
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