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参数资料
| 型号： | W3H128M72E-667SBM |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 1.25 ns, PBGA208 |
| 封装： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 28/32页 |
| 文件大小： | 988K |
| 代理商： | W3H128M72E-667SBM |
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W3H128M72E-XSBX
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE – 1 BALL DESCRIPTIONS
(continued)
A0-A13
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
DQ0-71
I/O
Data input/output: Bidirectional data bus
UDQS, UDQS#
I/O
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
LDQS, LDQS#
I/O
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
VCC
Supply
Power Supply: I/O + core, VCCQ is common to VCC
VREF
Supply
SSTL_18 reference voltage.
VSS
Supply
Ground
NC
-
No connect: These balls should be left unconnected.
DNU
-
Future use; address bits A14 and A15 are reserved for future densities.
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