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| 型号： | W3H128M72E-667SBM |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 1.25 ns, PBGA208 |
| 封装： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 8/32页 |
| 文件大小： | 988K |
| 代理商： | W3H128M72E-667SBM |
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W3H128M72E-XSBX
16
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
Function
CKE
CS#
RAS#
CAS#
WE#
BA2
BA1
BA0
A13
A12
A11
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
H
LLLL
BA
OP Code
2
REFRESH
H
L
H
XXXX
SELF-REFRESH Entry
H
L
H
XXXX
SELF-REFRESH Exit
LH
H
XXX
XXXX
7
L
HHH
Single bank precharge
HH
L
H
L
X
L
X
2
All banks PRECHARGE
HH
L
H
L
X
H
X
Bank activate
H
L
H
L
BA
Row Address
WRITE
HH
L
H
L
BA
Column
Address
L
Column
Address
2, 3
WRITE with auto precharge
HH
L
H
L
BA
Column
Address
H
Column
Address
2, 3
READ
H
LH
BA
Column
Address
L
Column
Address
2, 3
READ with auto precharge
H
LH
BA
Column
Address
H
Column
Address
2, 3
NO OPERATION
H
X
L
H
XXXX
Device DESELECT
H
X
H
XXXXXXX
POWER-DOWN entry
HL
H
XXX
XXXX
4
L
HHH
POWER-DOWN exit
LH
H
XXX
XXXX
4
L
HHH
Note: 1. All DDR2 SDRAM commands are dened by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a dened logic level).
7. Self refresh exit is asynchronous.
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