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| 型号： | W3H128M72E-667SBM |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 1.25 ns, PBGA208 |
| 封装： | 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 3/32页 |
| 文件大小： | 988K |
| 代理商： | W3H128M72E-667SBM |
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W3H128M72E-XSBX
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
CAS LATENCY (CL)
The CAS latency (CL) is dened by bits M4–M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of the
rst bit of output data. The CL can be set to 4, 5 or 6 clocks,
depending on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AL). This feature allows the READ
command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
An example of CL = 4 is shown in Figure 6; assume AL =
0. If a READ command is registered at clock edge n, and
the CL is m clocks, the data will be available nominally
coincident with clock edge n+m (this assumes AL = 0).
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal
t AC, tDQSCK, and tDQSQ
DON’T CARE
TRANSITIONING DATA
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
FIGURE 6 – CAS LATENCY (CL)
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