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参数资料
| 型号： | W3H32M72E-667SB2M |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| 封装： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 20/25页 |
| 文件大小： | 1062K |
| 代理商： | W3H32M72E-667SB2M |
W3H32M72E-XSB2X
November 2010 2010 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation (602) 437-1520 www.whiteedc.com
Rev. 3
www.microsemi.com
Microsemi Corporation reserves the right to change products or specications without notice.
TABLE 1 – BALL DESCRIPTIONS
Symbol
Type
Description
ODT
Input
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be
ignored if disabled via the LOAD MODE command.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM.
The specic circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conguration and operating mode. CKE
LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row
active in any bank). CKE is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry.
CKE is asynchronous for self refresh exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input
buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once
VCC is applied during rst power-up. After VREF has become stable during the power on and initialization sequence, it must be
maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, WE# (along with CS#) dene the command being entered.
LDM, UDM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during
a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match
that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4
BA0–BA1
Input
Bank address inputs: BA0–BA1 dene to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
BA0–BA1 dene which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
A0-A12
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10)
for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA1–BA0) or
all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD MODE command.
DQ0-71
I/O
Data input/output: Bidirectional data bus
UDQS, UDQS#
I/O
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
LDQS, LDQS#
I/O
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
VCC
Supply
Power Supply: 1.8V ±0.1V
VCCQ
Supply
DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity
VREF
Supply
SSTL_18 reference voltage.
VSS
Supply
Ground
NC
-
No connect: These balls should be left unconnected.
DNU
-
Future use; Row address bits A14 and A15 are reserved for 8Gb and 16Gb densities. BA2 is reserved for 4Gb device.
相关PDF资料 |
PDF描述 |
|---|---|
| W3H32M72E-667SBC | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| W3H64M16E-400BC | 64M X 16 DDR DRAM, 0.6 ns, PBGA79 |
| W3H64M64E-400SBC | 64M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3H32M72E-667SB2M/T/R | 制造商:Microsemi Corporation 功能描述:PBGA,32M X72,DDR2 SDRAM, 1.8V - Tape and Reel |
| W3H32M72E-667SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H32M72E-667SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-667SBM | 制造商:PMG/Microsemi 功能描述: |
| W3H32M72E-ES | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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