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参数资料
| 型号： | W3H32M72E-667SB2M |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| 封装： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 24/25页 |
| 文件大小： | 1062K |
| 代理商： | W3H32M72E-667SB2M |
W3H32M72E-XSB2X
November 2010 2010 Microsemi Corporation. All rights reserved.
8
Microsemi Corporation (602) 437-1520 www.whiteedc.com
Rev. 3
www.microsemi.com
Microsemi Corporation reserves the right to change products or specications without notice.
MODE REGISTER (MR)
The mode register is used to dene the specic mode of operation
of the DDR2 SDRAM. This denition includes the selection of a
burst length, burst type, CL, operating mode, DLL RESET, write
recovery, and power-down mode, as shown in Figure 5. Contents of
the mode register can be altered by re-executing the LOAD MODE
(LM) command. If the user chooses to modify only a subset of the
MR variables, all variables (M0–M14) must be programmed when
the command is issued.
The mode register is programmed via the LM command (bits
BA1–BA0 = 0, 0) and other bits (M12–M0) will retain the stored
information until it is programmed again or the device loses power
(except for bit M8, which is self-clearing). Reprogramming the
mode register will not alter the contents of the memory array,
provided it is performed correctly.
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts are in
progress. The controller must wait the specied time tMRD before
initiating any subsequent operations such as an ACTIVE command.
Violating either of these requirements will result in unspecied
operation.
BURST LENGTH
Burst length is dened by bits M0–M3, as shown in Figure 5. Read
and write accesses to the DDR2 SDRAM are burst-oriented, with
the burst length being programmable to either four or eight. The
burst length dete rmines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =
8 (where Ai is the most signicant column address bit for a given
conguration). The remaining (least signicant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved. The burst type is selected via bit M3,
as shown in Figure 5. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting
column address, as shown in Table 2. DDR2 SDRAM supports
4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,
full interleave address ordering is supported; however, sequential
address ordering is nibble-based.
OPERATING MODE
The normal operating mode is selected by issuing a command
with bit M7 set to “0,” and all other bits set to the desired values,
as shown in Figure 5. When bit M7 is “1,” no other bits of the
mode register are programmed. Programming bit M7 to “1” places
the DDR2 SDRAM into a test mode that is only used by the
Burst Length
CAS# Latency BT
PD
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
97
6
5
4
3
82
1
0
A10
A12 A11
BA0
BA1
BA2
10
11
12
13
01
14
Burst Length
Reserved
4
8
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
1
0
1
M2
0
1
0
1
Burst Type
Sequential
Interleaved
M3
CAS Laten cy (CL)
Reserved
3
4
5
6
Reserved
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
0
1
Mo de
Normal
Test
M7
15
16
DLL TM
0
1
DLL Reset
No
Yes
M8
WRITE RECOVERY
Reserved
2
3
4
5
6
Reserved
M9
0
1
0
1
0
1
0
1
M10
0
1
0
1
M11
0
1
WR
A13
MR
0
1
0
1
Mo de Register Definition
Mode Register (MR)
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
M15
0
1
M16
0
1
PD mode
Fast Exit
(Normal)
Slow Exit
(Low Power)
M12
M14
FIGURE 5 – MODE REGISTER (MR) DEFINITION
Note: 1. Not used on this part
manufacturer and should not be used. No operation or functionality
is guaranteed if M7 bit is ‘1.’
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DLL RESET function.
Bit M8 is self-clearing, meaning it returns back to a value of “0”
after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must
occur before a READ command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing
to wait for synchronization to occur may result in a violation of the
tAC or tDQSCK parameters.
WRITE RECOVERY
Write recovery (WR) time is dened by bits M9–M11, as shown in
Figure 5. The WR register is used by the DDR2 SDRAM during
WRITE with auto precharge operation. During WRITE with auto
precharge operation, the DDR2 SDRAM delays the internal auto
precharge operation by WR clocks (programmed in bits M9–M11)
from the last data burst.
相关PDF资料 |
PDF描述 |
|---|---|
| W3H32M72E-667SBC | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| W3H64M16E-400BC | 64M X 16 DDR DRAM, 0.6 ns, PBGA79 |
| W3H64M64E-400SBC | 64M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3H32M72E-667SB2M/T/R | 制造商:Microsemi Corporation 功能描述:PBGA,32M X72,DDR2 SDRAM, 1.8V - Tape and Reel |
| W3H32M72E-667SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H32M72E-667SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-667SBM | 制造商:PMG/Microsemi 功能描述: |
| W3H32M72E-ES | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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