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参数资料
| 型号： | W3H32M72E-667SB2M |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| 封装： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 25/25页 |
| 文件大小： | 1062K |
| 代理商： | W3H32M72E-667SB2M |
W3H32M72E-XSB2X
November 2010 2010 Microsemi Corporation. All rights reserved.
9
Microsemi Corporation (602) 437-1520 www.whiteedc.com
Rev. 3
www.microsemi.com
Microsemi Corporation reserves the right to change products or specications without notice.
TABLE 2 – BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column
within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column
within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting
column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
WR values of 2, 3, 4, 5, or 6 clocks may be used for programming
bits M9–M11. The user is required to program the value of WR,
which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding
up a non integer value to the next integer; WR [cycles] = tWR [ns] /
tCK [ns]. Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
POWER-DOWN MODE
Active power-down (PD) mode is dened by bit M12, as shown
in Figure 5. PD mode allows the user to determine the active
power-down mode, which determines performance versus power
savings. PD mode bit M12 does not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode or “fast-exit” active PD
mode is enabled. The tXARD parameter is used for fast-exit active
PD exit timing. The DLL is expected to be enabled and running
during this mode.
When bit M12 = 1, a lower-power active PD mode or “slow-exit”
active PD mode is enabled. The tXARD parameter is used for slow-
exit active PD exit timing. The DLL can be enabled, but “frozen”
during active PD mode since the exit-to-READ command timing is
relaxed. The power difference expected between PD normal and
PD low-power mode is dened in the ICC table.
CAS LATENCY (CL)
The CAS latency (CL) is dened by bits M4–M6, as shown in
Figure 5. CL is the delay, in clock cycles, between the registration
of a READ command and the availability of the rst bit of output
data. The CL can be set to 3, 4, 5, or 6 clocks, depending on the
speed grade option being used.
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal
t AC, tDQSCK, and tDQSQ
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
FIGURE 6 – CAS LATENCY (CL)
相关PDF资料 |
PDF描述 |
|---|---|
| W3H32M72E-667SBC | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| W3H64M16E-400BC | 64M X 16 DDR DRAM, 0.6 ns, PBGA79 |
| W3H64M64E-400SBC | 64M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3H32M72E-667SB2M/T/R | 制造商:Microsemi Corporation 功能描述:PBGA,32M X72,DDR2 SDRAM, 1.8V - Tape and Reel |
| W3H32M72E-667SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H32M72E-667SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-667SBM | 制造商:PMG/Microsemi 功能描述: |
| W3H32M72E-ES | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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