- 您现在的位置：买卖IC网 > PDF目录68559 > W9412G2CB-5 (WINBOND ELECTRONICS CORP) 4M X 32 DDR DRAM, 0.6 ns, PBGA144 PDF资料下载
参数资料
| 型号： | W9412G2CB-5 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 4M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封装： | 12 X 12 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-144 |
| 文件页数： | 34/49页 |
| 文件大小： | 1936K |
| 代理商： | W9412G2CB-5 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页当前第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页
W9412G2CB
Publication Release Date:Jul. 07, 2008
- 4 -
Revision A11
1. GENERAL DESCRIPTION
W9412G2CB is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 1,048,576 words
× 4 banks × 32 bits. Using pipelined architecture and 0.11 m
process technology, W9412G2CB delivers a data bandwidth of up to 400M words per second (-5). To
fully comply with the personal computer industrial standard, W9412G2CB is sorted into following
speed grades: -5/-5H, -6 and -75. The -5/-5H is compliant to the DDR400/CL3 specification. The -6 is
compliant to the DDR333/CL2.5 specification. The -75 is compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G2CB is ideal for any high
performance applications.
2. FEATURES
2.5V
±0.2V Power Supply for -5/-6/-75 speed grade
2.2V ~2.7V Power Supply for -5H speed grade
Up to 200 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6S Refresh interval (4K/64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in 144L LFBGA (12X12X1.40 mm^3, =0.5mm), using Pb free with RoHS compliant
相关PDF资料 |
PDF描述 |
|---|---|
| W9412G6IH-4 | 8M X 16 DDR DRAM, 0.65 ns, PDSO66 |
| W942508AH-8 | 32M X 8 DDR DRAM, 0.8 ns, PDSO66 |
| W942516AH-6 | 16M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W942516CH-75 | 16M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| W9425G6DH-6F | 16M X 16 DDR DRAM, 0.7 ns, PDSO66 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9412G2IB | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M × 4 BANKS × 32 BITS GDDR SDRAM |
| W9412G2IB4 | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture; two data transfers per clock cycle |
| W9412G2IB-5 | 制造商:Winbond Electronics Corp 功能描述:8*16 DDR1 |
| W9412G6CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:2M 】 4 BANKS 】 16 BITS DDR SDRAM |
| W9412G6IH | 制造商:WINBOND 制造商全称:Winbond 功能描述:2M × 4 BANKS × 16 BITS DDR SDRAM |
发布紧急采购，3分钟左右您将得到回复。