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| 型号： | W9425G6EH-5 |
| 厂商： | Winbond Electronics |
| 文件页数： | 7/54页 |
| 文件大小： | 0K |
| 描述： | IC DDR-400 SDRAM 256MB 66TSSOPII |
| 标准包装： | 108 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR SDRAM |
| 存储容量： | 256M（16Mx16） |
| 速度： | 250MHz |
| 接口： | 并联 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 66-TSSOP（0.400"，10.16mm 宽） |
| 供应商设备封装： | 66-TSOP II |
| 包装： | 托盘 |
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W9425G6EH
5. PIN DESCRIPTION
PIN NUMBER
28 ? 32,
35 ? 42
26, 27
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
16,51
PIN
NAME
A0 ? A12
BA0, BA1
DQ0 ?
DQ15
LDQS,
UDQS
FUNCTION
Address
Bank Select
Data Input/ Output
Data Strobe
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 ? A12.
Column address: A0 ? A8. (A10 is used for Auto-precharge)
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
24
23, 22, 21
20, 47
45, 46
CS
RAS ,
CAS , WE
LDM, UDM
CLK ,
CLK
Chip Select
Command Inputs
Write Mask
Differential Clock
Inputs
decoder is disabled, new command is ignored and previous
operation continues.
Command inputs (along with CS ) define the command
being entered.
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK .
CKE controls the clock activation and deactivation. When
44
CKE
Clock Enable
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
49
V REF
Reference Voltage V REF is reference voltage for inputs.
1, 18, 33
34, 48, 66
V DD
V SS
Power (+2.5V)
Ground
Power for logic circuit inside DDR SDRAM.
Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
V DDQ
Power (+2.5V) for Separated power from V DD , used for output buffer, to
I/O Buffer improve noise.
6, 12, 52, 58, 64
14, 17, 19, 25,
43, 50, 53
V SSQ
NC
Ground for I/O
Buffer
No Connection
Separated ground from V SS , used for output buffer, to
improve noise.
No connection (NC pin should be connected to GND or
floating)
Publication Release Date:Dec. 03, 2008
-7-
Revision A08
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9425G6EH-5I | 制造商:Winbond Electronics Corp 功能描述: |
| W9425G6JB-5 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 60-Pin TFBGA 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY 制造商:Winbond 功能描述:16MX16,256Mb DDRI DRAM ,200MHZ, BGA |
| W9425G6JB-5 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ |
| W9425G6JB-5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9425G6JB-5I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ, IN |
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