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参数资料
| 型号： | W9425G6JB-5 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封装： | 8 X 13 MM, ROHS COMPLIANT, TFBGA-60 |
| 文件页数： | 19/50页 |
| 文件大小： | 852K |
| 代理商： | W9425G6JB-5 |
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W9425G6JB
Publication Release Date: Oct. 08, 2010
- 26 -
Revision A01
9.6 AC Characteristics and Operating Condition
SYM.
PARAMETER
-5
UNIT
NOTES
MIN.
MAX.
tRC
Active to Ref/Active Command Period
55
nS
tRFC
Ref to Ref/Active Command Period
70
tRAS
Active to Precharge Command Period
40
70000
tRCD
Active to Read/Write Command Delay Time
15
tRAP
Active to Read with Auto-precharge Enable
15
tCCD
Read/Write(a) to Read/Write(b) Command Period
1
tCK
tRP
Precharge to Active Command Period
15
nS
tRRD
Active(a) to Active(b) Command Period
10
tWR
Write Recovery Time
15
tDAL
Auto-precharge Write Recovery + Precharge Time
(tWR/tCK) +
(tRP/tCK)
tCK
18
tCK
CLK Cycle Time
CL = 2
7.5
12
nS
CL = 2.5
6
12
CL = 3
5
12
tAC
Data Access Time from CLK, CLK
-0.7
0.7
16
tDQSCK
DQS Output Access Time from CLK, CLK
-0.6
0.6
16
tDQSQ
Data Strobe Edge to Output Data Edge Skew
0.4
tCH
CLk High Level Width
0.45
0.55
tCK
11
tCL
CLK Low Level Width
0.45
0.55
11
tHP
CLK Half Period (minimum of actual tCH, tCL)
Min. (tCL,tCH)
nS
tQH
DQ Output Data Hold Time from DQS
tHP-0.5
tRPRE
DQS Read Preamble Time
0.9
1.1
tCK
11
tRPST
DQS Read Postamble Time
0.4
0.6
11
tDS
DQ and DM Setup Time
0.4
nS
tDH
DQ and DM Hold Time
0.4
tDIPW
DQ and DM Input Pulse Width (for each input)
1.75
tDQSH
DQS Input High Pulse Width
0.35
tCK
11
tDQSL
DQS Input Low Pulse Width
0.35
11
tDSS
DQS Falling Edge to CLK Setup Time
0.2
11
tDSH
DQS Falling Edge Hold Time from CLK
0.2
11
tWPRES
Clock to DQS Write Preamble Set-up Time
0
nS
tWPRE
DQS Write Preamble Time
0.25
tCK
11
tWPST
DQS Write Postamble Time
0.4
0.6
11
tDQSS
Write Command to First DQS Latching Transition
0.72
1.25
11
tIS
Input Setup Time (fast slew rate)
0.6
nS
19, 21-23
tIH
Input Hold Time (fast slew rate)
0.6
19, 21-23
tIS
Input Setup Time (slow slew rate)
0.7
20-23
tIH
Input Hold Time (slow slew rate)
0.7
20-23
tIPW
Control & Address Input Pulse Width (for each input)
2.2
tHZ
Data-out High-impedance Time from CLK, CLK
0.7
tLZ
Data-out Low-impedance Time from CLK, CLK
-0.7
0.7
tT(SS)
SSTL Input Transition
0.5
1.5
tWTR
Internal Write to Read Command Delay
2
tCK
tXSNR
Exit Self Refresh to non-Read Command
75
nS
tXSRD
Exit Self Refresh to Read Command
200
tCK
tREFI
Refresh Time (8k/64mS)
7.8
S
17
tMRD
Mode Register Set Cycle Time
10
nS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9425G6JB-5 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ |
| W9425G6JB-5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9425G6JB-5I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ, IN |
| W9425G6JH | 制造商:WINBOND 制造商全称:Winbond 功能描述:4 M × 4 BANKS × 16 BITS DDR SDRAM |
| W9425G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 66-Pin TSOP-II 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY 制造商:Winbond 功能描述:16MX16,256MB DDR,250MHZ,2.5V , TSOP 66PIN GREEN |
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