参数资料
型号: W9425G6JB-5
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA60
封装: 8 X 13 MM, ROHS COMPLIANT, TFBGA-60
文件页数: 21/50页
文件大小: 852K
代理商: W9425G6JB-5
W9425G6JB
Publication Release Date: Oct. 08, 2010
- 28 -
Revision A01
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK)+VICK( CLK )}/2.
(15) Refer to the figure below.
CLK
VSS
VICK
VX
VICK
VID(AC)
0 V Differential
VISO
VISO(min)
VISO(max)
VSS
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
(18) tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For -5 speed grade at CL=2.5 and tCK=6 nS
tDAL = ((15 nS / 6 nS) + (15 nS / 6 nS)) clocks = ((3) + (3)) clocks = 6 clocks
(19) For command/address input slew rate ≥1.0 V/nS.
(20) For command/address input slew rate ≥0.5 V/nS and <1.0 V/nS.
(21) For CLK & CLK slew rate ≥1.0 V/nS (single--ended).
(22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
(23) Slew Rate is measured between VOH(ac) and VOL(ac).
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