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参数资料
| 型号： | W9425G6JB-5 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封装： | 8 X 13 MM, ROHS COMPLIANT, TFBGA-60 |
| 文件页数： | 48/50页 |
| 文件大小： | 852K |
| 代理商： | W9425G6JB-5 |
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W9425G6JB
Publication Release Date: Oct. 08, 2010
- 7 -
Revision A01
5. BALL DESCRIPTION
BALL NUMBER SYMBOL
FUNCTION
DESCRIPTION
K7, L8, L7, M8,
M2, L3, L2, K3,
K2, J3, K8, J2, H2
A0
A12
Address
Multiplexed pins for row and column address.
Row address: A0
A12.
Column address: A0
A8. (A10 is used for Auto-precharge)
J8, J7
BA0, BA1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
A8, B9, B7, C9,
C7, D9, D7, E9,
E1, D3, D1, C3,
C1, B3, B1, A2
DQ0
DQ15
Data Input/ Output
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
E7, E3
LDQS,
UDQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
H8
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
H7, G8, G7
RAS ,
CAS , WE
Command Inputs Command inputs (along with CS ) define the command
being entered.
F7, F3
LDM, UDM
Write Mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
G2, G3
CLK,
CLK
Differential Clock
Inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK
.
H3
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
F1
VREF
Reference Voltage VREF is reference voltage for inputs.
F8, M7, A7
VDD
Power (+2.5V)
Power for logic circuit inside DDR SDRAM.
A3, F2, M3
VSS
Ground
Ground for logic circuit inside DDR SDRAM.
B2, D2, C8, E8,
A9
VDDQ
Power (+2.5V) for
I/O Buffer
Separated power from VDD, used for output buffer, to
improve noise.
A1, C2, E2, B8,
D8
VSSQ
Ground for I/O
Buffer
Separated ground from VSS, used for output buffer, to
improve noise.
F9
NC
No Connection
No connection
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9425G6JB-5 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ |
| W9425G6JB-5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9425G6JB-5I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ, IN |
| W9425G6JH | 制造商:WINBOND 制造商全称:Winbond 功能描述:4 M × 4 BANKS × 16 BITS DDR SDRAM |
| W9425G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 66-Pin TSOP-II 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY 制造商:Winbond 功能描述:16MX16,256MB DDR,250MHZ,2.5V , TSOP 66PIN GREEN |
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