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Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Port Config
Reserved
Link
Disable
Txmit
Disable
Bypass
Scrambler
(100BASE
-TX)
Bypass
4B/5B
(100BAS
E-TX)
Jabber
(10T)
SQE
(10T)
TP
Loopback
(10T)
Reserved
PRE_EN
Reserved
Far End
Fault
Enable
Reserved
Fiber
Select
16
Quick Status Register (Address 17)
Quick Status
Reserved
10/100
Mode
Transmit
Status
Receiver
Status
Collision
Status
Link
Duplex
Mode
Auto-Neg
Complete
FIFO Error
Polarity
Pause
Error
Reserved
17
Interrupt Enable Register (Address 18)
Interrupt
Enable
Reserved
Counter
Mask
Auto-Neg
Mask
Speed
Mask
Duplex
Mask
Link Mask
Isolate
Mask
Reserved
Interrupt
Enable
Test
Interrupt
18
Interrupt Status Register (Address 19)
Interrupt
Status
Reserved
RxER
Counter
Full
Auto-Neg
Done
Speed
Change
Duplex
Change
Link
Change
Isolate
Change
MD
Interrupt
Reserved
19
LED Configuration Register (Address 20)
LED Config
LED1
LED2
LED3
LED Freq
Pulse
Stretch
Reserved
20
Receive Error Count Register (Address 21)
Rcv Error
Count
Receive Error Count
21
Programmable RMII Out-of-Band Signaling Register (Register 25)
RMII OOB
Signaling
Reserved
Bit 1
Bit 0
Program
RMII
25
Trim Enable Register (Address 27)
Trim Enable
Reserved
Per Port Rise Time
Control
AMDIX_EN
MDIX
Analog
Loopback
Dis_EN
Loop Back
Speed Up
Enable
Power_EN
SLP_Det
LFIT
Expired
Reserved
27
Cable Diagnostics Register (Address 29)
Cable
Diagnostics
Reserved
Start-Test
CD_EN
Test-Done
Fault_
Type
Line Fault Counter
29
Table 102
Register Bit Map
Reg Title
Bit Fields
Addr
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0