- 您现在的位置：买卖IC网 > PDF目录68561 > WBLXT9785HCD0SE001 (CORTINA SYSTEMS INC) DATACOM, INTERFACE CIRCUIT, PQFP208 PDF资料下载
参数资料
| 型号： | WBLXT9785HCD0SE001 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| 封装： | ROHS COMPLIANT, PLASTIC, QFP-208 |
| 文件页数： | 67/221页 |
| 文件大小： | 3113K |
| 代理商： | WBLXT9785HCD0SE001 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页当前第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页
Page 159
Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.14 Link Hold-Off Overview
4.14
Link Hold-Off Overview
The PHY link is established as soon as the system platform powers-up. In many cases,
the system platform is not capable of supporting network operation until configuration
firmware is loaded. It is desirable in such cases to prevent the PHY from establishing a
link until the system platform is fully configured and ready for network operation. Link
Hold-Off was incorporated into the LXT9785/LXT9785E device to satisfy these
requirements. Enabling Link Hold-Off disables the PHY Link capability until the system
platform is fully capable of supporting network operation. The feature is enabled by
hardware control at power-up or software control during normal operation.
4.14.1
Features
Link Hold-Off prevents the LXT9785/LXT9785E from establishing a link by disabling the
analog transmit and receive capability. The digital capabilities of the PHY are unaffected
including register access and LED operation. Link Hold-Off can be enabled by an external
hardware pin for all ports or by software register access for individual ports. When Link
Hold-Off is enabled, the transmitter and receiver on the selected ports are forced into
software power-down mode (see Section 4.5.3, Power-Down Mode, on page 124) to block
signal activity from establishing a link and passing packets through the PHY.
The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-
down resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin
enables the feature at power-up reset or external hardware pin Reset. Once a PHY port is
programmed as desired, clearing Register bit 0.11 will re-enable that port. Each port must
be individually re-enabled.
When a port is software reset, by setting Register 0.15, the state of the hardware
configuration pin captured by the last hardware or power-up reset determines the default
register values for the specific function for that port. Link Hold-Off, once enabled by
hardware configuration, is re-enabled on a port by issuing a software reset for that port. It
is not necessary to reset the entire PHY or switch system to re-enable Link Hold-Off.
Link Hold-Off software control is enabled or disabled on individual ports by respectively
setting or clearing Register bit 0.11, the power-down bit, during normal operation. It is not
required to have previously enabled Link Hold-Off by hardware configuration.
Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the
MDIO interface required to re-enable normal transmit and receive link operation. MDDIS
is intended to disable the MDIO management interface for unmanaged applications.
Internal loopback circuitry is unaffected in Link Hold-Off mode.
4.14.2
Operation
Link Hold-Off is implemented in one of the following two ways:
Using a hardware pin at power-up or hardware reset
Using software control through the MII Management (MDC/MDIO) interface.
Link Hold-Off use by an external hardware pin is as follows:
1. Pull the LINKHOLD pin High with a pull-up resistor (approximately 5 k Ohms).
2. Power up the system or drive the reset pin active.
3. All ports are link disabled.
4. Program all ports to the desired configuration.
相关PDF资料 |
PDF描述 |
|---|---|
| WBLXT9785HEC2VSE000 | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| WBLXT9785HEC2VSE001 | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| WBLXT9785HED0SE000 | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| WBLXT9785HED0SE001 | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| WBLXT9785EHCC2V | DATACOM, INTERFACE CIRCUIT, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WBLXT9785HE.D0-865114 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBM-DATA | 制造商:Thomas & Betts 功能描述: |
| WBM-DISHWASH | 制造商:Thomas & Betts 功能描述: |
| WBM-DISPOSAL | 制造商:Thomas & Betts 功能描述: |
| WBM-DUPLEX | 制造商:Thomas & Betts 功能描述: |
发布紧急采购，3分钟左右您将得到回复。