参数资料
| 型号： | XA3S400A-4FGG400I |
| 厂商： | Xilinx Inc |
| 文件页数： | 57/57页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3A 400K 400-FBGA |
| 产品培训模块： | Extended Spartan 3A FPGA Family |
| 标准包装： | 60 |
| 系列： | Spartan®-3A XA |
| LAB/CLB数： | 896 |
| 逻辑元件/单元数： | 8064 |
| RAM 位总计： | 368640 |
| 输入/输出数： | 311 |
| 门数： | 400000 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 400-BGA |
| 供应商设备封装： | 400-FBGA（21x21） |
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XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
9
General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol
Description
Test Conditions
Min
Typ
Max
Units
IL(2)
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN =0V or VCCO max, sample-tested
–10
–
+10
A
IHS
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
A
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
Add IHS + IRPU
A
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.
VIN = GND
VCCO or VCCAUX =
3.0V to 3.6V
–151
–315
–710
A
VCCO or VCCAUX =
2.3V to 2.7V
–82
–182
–437
A
VCCO = 1.7V to 1.9V
–36
–88
–226
A
VCCO = 1.4V to 1.6V
–22
–56
–148
A
VCCO = 1.14V to 1.26V
–11
–31
–83
A
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
VIN = GND
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
k
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
k
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
k
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
k
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
k
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
VIN = VCCO
VCCAUX = 3.0V to 3.6V
167
346
659
A
VCCAUX = 2.25V to 2.75V
100
225
457
A
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
VCCAUX = 3.0V to 3.6V
VIN = 3.0V to 3.6V
5.5
10.4
20.8
k
VIN = 2.3V to 2.7V
4.1
7.8
15.7
k
VIN = 1.7V to 1.9V
3.0
5.7
11.1
k
VIN = 1.4V to 1.6V
2.7
5.1
9.6
k
VIN = 1.14V to 1.26V
2.4
4.5
8.1
k
VCCAUX = 2.25V to 2.75V
VIN = 3.0V to 3.6V
7.9
16.0
35.0
k
VIN = 2.3V to 2.7V
5.9
12.0
26.3
k
VIN = 1.7V to 1.9V
4.2
8.5
18.6
k
VIN = 1.4V to 1.6V
3.6
7.2
15.7
k
VIN = 1.14V to 1.26V
3.0
6.0
12.5
k
IREF
VREF current per pin
All VCCO levels
–10
–
+10
A
CIN
Input capacitance
–3
–10
pF
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
VCCO = 3.3V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
VCCO = 2.5V ± 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Notes:
1.
The numbers in this table are based on the conditions set forth in Table 8.
2.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide.
3.
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD =VIN /IRPD.
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