参数资料
| 型号： | XCV405E-7FG676C |
| 厂商： | Xilinx Inc |
| 文件页数： | 26/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 2400 |
| 逻辑元件/单元数： | 10800 |
| RAM 位总计： | 573440 |
| 输入/输出数： | 404 |
| 门数： | 129600 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
11
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (05 for Virtex-E family)
a = the number of CLB rows (ranges from 16 for
XCV50E to 104 for XCV3200E)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see Table 7) is embedded in the bitstream during bit-
stream generation and is valid only after configuration.
Note:
Attempting to load an incorrect bitstream causes
configuration to fail and can damage the device.
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special ele-
ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
Development System
Virtex-E FPGAs are supported by the Xilinx Foundation and
Alliance Series CAE tools. The basic methodology for Vir-
tex-E design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation (for example,
Synopsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.
The Xilinx development system is integrated under the
Xilinx Design Manager (XDM) software, providing design-
ers with a common user interface regardless of their choice
of entry and verification tools. The XDM software simplifies
the selection of implementation options with pull-down
menus and on-line help.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM software. The program command sequence is gener-
ated prior to execution, and stored for documentation.
Several advanced software features facilitate Virtex-E design.
RPMs, for example, are schematic-based macros with relative
location constraints to guide their placement. They help
ensure optimal implementation of common functions.
For HDL design entry, the Xilinx FPGA Foundation develop-
ment system provides interfaces to the following synthesis
design environments.
Synopsys (FPGA Compiler, FPGA Express)
Exemplar (Spectrum)
Synplicity (Synplify)
For schematic design entry, the Xilinx FPGA Foundation
and Alliance development system provides interfaces to the
following schematic-capture design environments.
Mentor Graphics V8 (Design Architect, QuickSim II)
Viewlogic Systems (Viewdraw)
Third-party vendors support many other environments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Virtex-E FPGAs are supported by a unified library of stan-
dard functions. This library contains over 400 primitives and
macros, ranging from 2-input AND gates to 16-bit accumu-
lators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
The “soft macro” portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
RPMs, on the other hand, do contain predetermined parti-
tioning and placement information that permits optimal
implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are auto-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entry method to
be used for each portion of the design.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
Table 7:
IDCODEs Assigned to Virtex-E FPGAs
FPGA
IDCODE
XCV405EM
v0C28093h
XCV812EM
v0C38093h
相关PDF资料 |
PDF描述 |
|---|---|
| BR93L86RFVT-WE2 | IC EEPROM 16KBIT 2MHZ 8TSSOP |
| XCV405E-6FG676I | IC FPGA 1.8V 676-BGA |
| BR93L86RFVM-WTR | IC EEPROM 16KBIT 2MHZ 8MSOP |
| BR93L86RFV-WE2 | IC EEPROM 16KBIT 2MHZ 8SSOP |
| BR25L020FV-WE2 | IC EEPROM SER 2KB SPI BUS 8SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV405E-7FG676I | 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-E EM 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV405E-7FG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7FG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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