参数资料
型号: XCV405E-7FG676C
厂商: Xilinx Inc
文件页数: 63/118页
文件大小: 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
产品变化通告: FPGA Family Discontinuation 18/Apr/2011
标准包装: 1
系列: Virtex®-E EM
LAB/CLB数: 2400
逻辑元件/单元数: 10800
RAM 位总计: 573440
输入/输出数: 404
门数: 129600
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
45
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
LVDS
Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrat-
ing a valid termination technique for transmitting LVDS sig-
nals appears in Figure 54. A sample circuit illustrating a
valid termination for receiving LVDS signals appears in
Figure 55. Table 38 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
LVPECL
Depending on whether the device is transmitting or receiv-
ing an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid ter-
mination
technique
for
transmitting
LVPECL
signals
appears in Figure 56. A sample circuit illustrating a valid ter-
mination
for
receiving
LVPECL
signals
appears
in
Figure 57. Table 39 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Figure 54: Transmitting LVDS Signal Circuit
Figure 55: Receiving LVDS Signal Circuit
Table 38:
LVDS Voltage Specifications
Parameter
Min
Typ
Max
VCCO
2.375
2.5
2.625
VICM(2)
0.2
1.25
2.2
VOCM(1)
1.125
1.25
1.375
VIDIFF (1)
0.1
0.35
-
VODIFF (1)
0.25
0.35
0.45
VOH(1)
1.25
-
VOL(1)
-
1.25
Notes:
1.
Measured with a 100
Ω resistor across Q and Q.
2.
Measured with a differential input voltage =
+/ 350 mV.
x133_19_122799
Q
Z0 = 50Ω
Q
Virtex-E
FPGA
to LVDS Receiver
RDIV
140
R
S
165
R
S
165
2.5V
V
CCO = 2.5V
LVDS
Output
DATA
Transmit
1/4 of Bourns
Part Number
CAT16-LV4F12
x133_29_122799
Q
Z0 = 50Ω
LVDS_IN
Z0 = 50Ω
R
T
100
Ω
Q
DATA
Receive
from
LVDS
Driver
VIRTEX-E
FPGA
+
Figure 56: Transmitting LVPECL Signal Circuit
Figure 57: Receiving LVPECL Signal Circuit
Table 39:
LVPECL Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF
--
-
VTT
--
-
VIH
1.49
-
2.72
VIL
0.86
-
2.125
VOH
1.8
-
VOL
-
1.57
Note: For more detailed information, see LVPECL DC
x133_20_122799
Q
Z0 = 50Ω LVPECL_OUT
LVPECL_OUT
Z0 = 50Ω
Q
Virtex-E
FPGA
to LVPECL Receiver
RDIV
187
R
S
100
R
S
100
3.3V
DATA
Transmit
1/4 of Bourns
Part Number
CAT16-PC4F12
x133_21_122799
Q
Z0 = 50Ω
LVPECL_IN
Z0 = 50Ω
R
T
100
Ω
Q
DATA
Receive
from
LVPECL
Driver
VIRTEX-E
FPGA
+
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