XR16V798
23
REV. 1.0.1
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
3.1.1.1
INT0 Channel Interrupt Indicator:
3.1.1.2
INT1, INT2 and INT3 Interrupt Source Locator
INT3, INT2 and INT1 provide a 24-bit (3 bits per channel) encoded interrupt indicator. Table 9 shows the 3 bit
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt.
For other channels, interrupt 7 is reserved.
.
FIGURE 13. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
TABLE 9: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY
Bit
2
Bit
1
Bit
0
INTERRUPT SOURCE(S) AND CLEARING
x
0
None or wake-up indicator
1
0
1
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
2
0
1
0
RXRDY Time-out: Cleared same way as RXRDY INT.
3
0
1
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
4
1
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clears after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR
register.
5
1
0
1
Reserved.
6
1
0
Reserved.
7
1
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
Reserved in other channels.
INT0 Register
Individual UART Channel Interrupt Status
Ch-7
Ch-6
Ch-5
Ch-4
Ch-3
Ch-2
Ch-1
Ch-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Channel-7
Channel-6
Channel-5
Channel-4
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
INT0 Register
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-6
Ch-7
Ch-5 Ch-4
Ch-1 Ch-0
Ch-3 Ch-2