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参数资料
| 型号： | XR16V798IQ-0B-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 37/56页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR16V798-B 100QFP |
| 设计资源： | XR17V798/794 Eval Board Schematic |
| 标准包装： | 1 |
| 系列： | * |
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XR16V798
42
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/
DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level
and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will re-
assert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-
7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection
for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when
hardware flow control is disabled.
Logic 0 = Automatic RTS/DTR flow control is disabled (default).
Logic 1 = Enable Automatic RTS/DTR flow control.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the enhanced functions in IER bits 7:5, ISR bits 5:4, FCR bits
5:4, MCR bits 7:5, 3:2 and MSR 7:2 bits to be modified. After modifying any enhanced bits, EFR bit-4 can be
set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the
enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 7:5, ISR bits 5:4, FCR bits 5:4, MCR bits 7:5,
3:2 and MSR 7:2 bits are saved to retain the user settings. After a reset, all these bits are set to a logic 0 to
be compatible with ST16C550 mode (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
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| XR16V798IQ-0A-EVB | EVAL BOARD FOR XR16V798-A 100QFP |
| XR16V698IQ-0B-EVB | EVAL BOARD FOR XR16V698-B 100QFP |
| XR16V698IQ-0A-EVB | EVAL BOARD FOR XR16V698-A 100QFP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16V798IQ-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V798IQTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 2.5V/3.3V 100-Pin PQFP T/R |
| XR-1790 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Audio Schematic |
| XR17C152 | 制造商:EXAR 制造商全称:EXAR 功能描述:5V PCI BUS DUAL UART |
| XR17C152CM | 制造商:EXAR 制造商全称:EXAR 功能描述:5V PCI BUS DUAL UART |
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