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参数资料
| 型号： | XR16V798IQ-0B-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 31/56页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR16V798-B 100QFP |
| 设计资源： | XR17V798/794 Eval Board Schematic |
| 标准包装： | 1 |
| 系列： | * |
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XR16V798
37
REV. 1.0.1
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic
1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity,
framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
LSR[6]: Transmitter Empty Flag
This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR,
in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the
TX FIFO or TSR contains a data character.
LSR[5]: Transmit FIFO Empty Flag
This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new
character for transmission. This bit is set to a logic 1 when the last data byte is transferred from the transmit
FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the transmit
FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is cleared when
at a byte is written to the THR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or logic 1.
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[2]: Receive Data Parity Error Flag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity
information and is suspect. This error is associated with the character available for reading in RHR.
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| XR16V698IQ-0A-EVB | EVAL BOARD FOR XR16V698-A 100QFP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16V798IQ-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V798IQTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 2.5V/3.3V 100-Pin PQFP T/R |
| XR-1790 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Audio Schematic |
| XR17C152 | 制造商:EXAR 制造商全称:EXAR 功能描述:5V PCI BUS DUAL UART |
| XR17C152CM | 制造商:EXAR 制造商全称:EXAR 功能描述:5V PCI BUS DUAL UART |
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