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参数资料
| 型号： | XR16V798IQ-0B-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 56/56页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR16V798-B 100QFP |
| 设计资源： | XR17V798/794 Eval Board Schematic |
| 标准包装： | 1 |
| 系列： | * |
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XR16V798
9
REV. 1.0.1
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
2.6
Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data
bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value
of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during
initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and
the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented
and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming
the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data
rate. Table 4 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate.
If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 4. At
8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-
time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-
standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
The closest divisor that is obtainable in the 798 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE [7:0] IS 0
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE [7:0] IS 1
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
FIGURE 4. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X
Sampling
Rate Clock
to Transmitter
and Receiver
To Other
Channels
Fractional Baud
Rate Generator
Logic
相关PDF资料 |
PDF描述 |
|---|---|
| XR16V798IQ-0A-EVB | EVAL BOARD FOR XR16V798-A 100QFP |
| XR16V698IQ-0B-EVB | EVAL BOARD FOR XR16V698-B 100QFP |
| XR16V698IQ-0A-EVB | EVAL BOARD FOR XR16V698-A 100QFP |
| KIT33972AEWEVBE | KIT EVALUATION FOR MC33972 |
| EBM31DCMS | CONN EDGECARD 62POS .156 WW |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16V798IQ-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V798IQTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 2.5V/3.3V 100-Pin PQFP T/R |
| XR-1790 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Audio Schematic |
| XR17C152 | 制造商:EXAR 制造商全称:EXAR 功能描述:5V PCI BUS DUAL UART |
| XR17C152CM | 制造商:EXAR 制造商全称:EXAR 功能描述:5V PCI BUS DUAL UART |
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