参数资料
| 型号： | XRD98L61AIV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 17/38页 |
| 文件大小： | 0K |
| 描述： | IC CCD DIGITIZER 12BIT 48TQFP |
| 标准包装： | 250 |
| 位数： | 12 |
| 通道数： | 1 |
| 电压 - 电源，模拟： | 2.7 V ~ 3.6 V |
| 电压 - 电源，数字： | 2.7 V ~ 3.6 V |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
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XRD98L61
24
Rev. 2.00
OB PIXEL CALIBRATION
Line Mode Calibration
In the Line mode, OB pixels are sampled when CAL is
active. CAL can be programmed to be active high or
active low. Please see the Timing section for more
details about clock polarity. Averaging will span as
many lines as needed to get the number of OB pixels
programmed by AVG[2:0]. Updates to the offset DACs
occur during the Optical Black pixel time after a
complete iteration. A complete iteration includes the
pixel clipping, averaging, calculation of the offset dif-
ference, and calculation of the DAC update values.
After a complete iteration, the averager is reset, and
the logic waits for the number of lines programmed in
the “Wait A” & “Wait B” registers (WL[11:0]) before
starting the next iteration.
Figure 12. Clock Polarity and Aperture Delays
CLOCK BASICS
There are five clock signals: SBLK, SPIX, ADCLK,
CLAMP, and CAL.
The pixel rate clocks are SBLK, SPIX, and ADCLK.
SBLK controls sampling of the Black reference level
for each pixel. SPIX controls sampling of the Video
level for each pixel. ADCLK controls the ADC sam-
pling the PGA output.
Polarity
SBLK
SPIX
ADCLK
CAL
CLAMP
Aperture
Delays
Clock Logic
AFE
ADC
Calibration
CLOCK POLARITY
Each of the five clocks has a separate polarity control
bit in the Polarity register. If the polarity bit for a clock
is low, then the clock is active low. If the polarity bit for
a clock is high, then the clock is active high. After reset
(by POR, reset bit or reset pin), all clocks default to
active low.
Manual Mode
The purpose of this mode is to disable the automatic
calibration feature. This allows manual adjustment of
offset in applications such as digital copiers and high
speed scanners. In Manual mode, the Coarse accu-
mulator is programmed by writing to the CDAC register;
the Fine accumulator is programmed by writing to the
FDAC register. The Coarse accumulator is a 9 bit
register. The Fine accumulator is a 10 bit register.
To activate the Manual mode, write a ”1” to the ManCal
bit in the Calibration register. By default, the Manual
mode is not active.
The line rate clocks are CLAMP & CAL.
CLAMP
controls the DC restore function for the external AC
coupling capacitors.
CAL controls the Black level
calibration by defining the OB pixels at the start or end
of each line.
In the One Shot mode (CAL only),
CLAMP is used to define the vertical shift period
between lines.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRD98L61EVAL | 功能描述:数据转换 IC 开发工具 Eval Board for XRD98L61AIV RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| XRD98L61ZEVAL | 功能描述:数据转换 IC 开发工具 Eval Board (Solder) XRD98L61AIV RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| XRD98L62 | 制造商:EXAR 制造商全称:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L62ACV | 制造商:EXAR 制造商全称:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L62ACV-F | 功能描述:视频 IC RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
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