参数资料
型号: XRT86VL30IV80-F
厂商: Exar Corporation
文件页数: 111/175页
文件大小: 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 80LQFP
标准包装: 90
控制器类型: T1/E1/J1 调帧器,LIU
电源电压: 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 托盘
其它名称: 1016-1486
XRT86VL30IV80-F-ND
XRT86VL30
35
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. 1.0.1
1
SB_ENB(1)
R/w
0
Receive Slip Buffer Mode Select
These bits select modes of operation for the receive slip buffer. These two
bits also select the direction of RxSERCLK and RxSYNC in base clock rate
(2.048MHz). The following table shows the corresponding slip buffer modes
as well as the direction of the RxSYNC/RxSERCLK according to the setting
of these two bits.
NOTE: Users must make sure that the RxSerClk input pin is synchronized to
the Recovered Clock signal for this particular channel to prevent any
buffer slips from occurring.
0
SB_ENB(0)
R/W
1
TABLE 21: FIFO LATENCY REGISTER (FFOLR)
HEX ADDRESS: 0X0117
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-5
Reserved
-
Reserved
4-0
Rx Slip Buffer FIFO
Latency[4:0]
R/W
00100
Receive Slip Buffer FIFO Latency[4:0]:
These bits permit the user to specify the “Receive Data” Latency (in
terms of RxSerClk_n clock periods), whenever the Receive Slip
Buffer has been configured to operate in the “FIFO” Mode.
NOTE: These bits are only active if the Receive Slip Buffer has been
configured to operate in the FIFO Mode.
TABLE 20: SLIP BUFFER CONTROL REGISTER (SBCR)
HEX ADDRESS: 0X0116
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
SB_ENB
[1:0]
RECEIVE SLIP BUFFER
MODE SELECT
DIRECTION OF
RXSERCLK
DIRECTION OF
RXSYNC
00/11
Receive Slip Buffer is
bypassed
Output
01
Slip Buffer Mode
Input
Depends on the
setting of SB_SDIR
(bit 2 of this register)
If SB_SDIR = 0:
RxSYNC = Output
If SB_SDIR = 1:
RxSYNC = Input
10
FIFO Mode.
FIFO data latency
can be programmed
by the 'FIFO Latency
Register' (Address =
0x0117).
Input
Depends on the
setting of SB_SDIR
(bit 2 of this register)
If SB_SDIR = 0:
RxSYNC = Output
If SB_SDIR = 1:
RxSYNC = Input
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