参数资料
型号: XRT86VL30IV80-F
厂商: Exar Corporation
文件页数: 26/175页
文件大小: 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 80LQFP
标准包装: 90
控制器类型: T1/E1/J1 调帧器,LIU
电源电压: 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 托盘
其它名称: 1016-1486
XRT86VL30IV80-F-ND
XRT86VL30
116
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
4
SLC
96 LOCK
RO
0
SLC
96 is in SYNC
This READ ONLY bit field indicates whether or not frame synchroni-
zation is achieved when the XRT86VL30 is configured in SLC
96
framing mode.
0 = Indicates that frame synchronization is not achieved in SLC
96
framing mode.
1 = Indicates that frame synchronization is achieved in SLC
96
framing mode.
3
Multiframe LOCK
RO
0
Multiframe is in SYNC
This READ ONLY bit field indicates whether or not the T1 Receive
Framer Block is declaring T1 Multiframe LOCK status.
0 = Indicates that the T1 Receive Framer is currently declaring T1
multiframe LOSS OF LOCK status
0 = Indicates that the T1 Receive Framer is currently declaring T1
multiframe LOCK status
2
RxSB_FULL
RUR/
WC
0
Receive Slip buffer Full Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receive Slip
Buffer Full interrupt has occurred since the last read of this register.
The Receive Slip Buffer Full interrupt is declared when the receive
slip buffer is filled. If the receive slip buffer is full and a WRITE oper-
ation occurs, then a full frame of data will be deleted, and this inter-
rupt bit will be set to ‘1’.
0 = Indicates that the Receive Slip Buffer Full interrupt has not
occurred since the last read of this register.
1 = Indicates that the Receive Slip Buffer Full interrupt has occurred
since the last read of this register.
TABLE 102: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR)
HEX ADDRESS: 0X0B08
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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