参数资料
型号: XRT86VL30IV80-F
厂商: Exar Corporation
文件页数: 67/175页
文件大小: 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 80LQFP
标准包装: 90
控制器类型: T1/E1/J1 调帧器,LIU
电源电压: 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 托盘
其它名称: 1016-1486
XRT86VL30IV80-F-ND
XRT86VL30
154
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3
NLCD_n
RO
0
Network Loop-Code Detection Status Bit:
This bit operates differently in the Manual or the Automatic Network
Loop-Code detection modes.
Manual Loop-Up Code detection mode
(.i.e If NLCDE1 = “0” and NLCDE0 = “1”), this bit gets set to “1” as
soon as the Loop-Up Code (“00001”) is detected in the receive data
for longer than 5 seconds.
This bit stays high as long as the Receive T1 LIU Block detects the
presence of the Loop-Up code in the receive data and it is reset to
“0” as soon as it stops receiving the Loop-Up Code.
If the NLCD interrupt is enabled, the XRT86VL30 will initiate an
interrupt on every transition of the NLCD status bit.
Manual Loop-Down Code detection mode
(i.e., If NLCDE1 = “1” and NLCDE0 = “0”), this bit gets set to “1” as
soon as the Loop-Down Code (“001”) is detected in the receive data
for longer than 5 seconds.
This bit stays high as long as the Receive T1 LIU Block detects the
presence of the Loop-Down code in the receive data and it is reset
to “0” as soon as it stops receiving the Loop-Down Code.
If the NLCD interrupt is enabled, the XRT86VL30 will initiate an
interrupt on every transition of the NLCD status bit.
Automatic Loop-code detection mode
(i.e., If NLCDE1 = “1” and NLCDE0 =”1”), the state of the NLCD sta-
tus bit is reset to “0” and the XRT86VL30 is programmed to monitor
the receive input data for the Loop-Up code.
This bit is set to a “1” to indicate that the Network Loop Code is
detected for more than 5 seconds. Simultaneously, the Remote
Loop-Back condition is automatically activated and the XRT86VL30
is programmed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays ‘high’ as long as the Remote Loop-
Back condition is in effect even if the chip stops receiving the Loop-
Up code. Remote Loop-Back is removed only if the XRT86VL30
detects the Loop-Down Code “001” pattern for longer than 5 sec-
onds in the receive data. Upon detecting the Loop-Down Code “001”
pattern, the XRT86VL30 will reset the NLCD status bit and an inter-
rupt will be generated if the NLCD interrupt enable bit is enabled.
Users can monitor the state of this bit to determine if the Remote
Loop-Back is activated.
2
Reserved
-
0
This Bit Is Not Used
1
RLOS_n
RO
0
Receive Loss of Signal Defect Condition Status:
This READ-ONLY bit indicates whether or not the Receive LIU Block
is currently declaring the LOS defect condition.
0 = Indicates that the Receive Section is NOT currently declaring
the LOS Defect Condition.
1 = Indicates that the Receive Section is currently declaring the LOS
Defect condition.
NOTE: If the RLOSIE bit (bit D1 of Register 0x0F04) is enabled, any
transition on this bit will generate an Interrupt.
TABLE 132: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR)
HEX ADDRESS: 0X0F05
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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