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参数资料
| 型号： | ZL2101ALAF |
| 厂商： | Intersil |
| 文件页数： | 14/27页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 36QFN |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.54 V ~ 5.5 V |
| 输入电压： | 4.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
| 供应商设备封装： | 36-QFN（6x6） |
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ZL2101
The soft-start delay period begins when the EN pin is asserted
and ends when the delay time expires. The soft-start delay period
is set using the SS pin. Precise ramp delay timing mode reduces
the delay time variations and is available when the appropriate
bit in the MISC_CONFIG register had been set. Please refer to
R SS
(k Ω )
10
TABLE 6. DELAY AND RAMP CONFIGURATION
DELAY TIME RAMP TIME UVLO
(ms) (ms) (V)
5
Application Note AN2033 for details.
11
10
5
The soft-start ramp timer enables a precisely controlled ramp to
the nominal V OUT value that begins once the delay period has
expired. The ramp-up is guaranteed monotonic and its slope may
be precisely set using the SS pin. Using the pin-strap method, the
soft-start delay and ramp times can be set to one of three
standard values according to Table 5.
TABLE 5. SOFT-START DELAY AND RAMP SETTINGS
DELAY AND
RAMP TIME
SS PIN SETTING (ms) UVLO
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
20
5
10
20
5
10
20
5
10
10
2
5
4.5
LOW
OPEN
HIGH
2
5
10
7.5V
28.7
31.6
34.8
38.3
20
5
10
20
10
5.5
If the desired soft-start delay and ramp times are not one of the
42.2
5
values listed in Table 5, the times can be set to a custom value by
connecting a resistor from the SS pin to SGND using the
appropriate resistor value from Table 6. The value of this resistor
is measured upon start-up or Restore and will not change if the
resistor is varied after power has been applied to the ZL2101
(see Figure 15).
ZL
R SS
FIGURE 15. SS PIN RESISTOR CONNECTIONS
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
110
121
133
147
162
10
20
5
10
20
5
10
20
5
10
20
5
10
20
20
2
5
10
20
7.5
The soft-start delay and ramp times can also be set to custom
values via the I 2 C/SMBus interface. When the SS delay time is
set to 0ms, the device will begin its ramp-up after the internal
circuitry has initialized (~2ms). When the soft-start ramp period
is set to 0ms, the output will ramp up as quickly as the output
load capacitance and loop settings will allow. It is generally
recommended to set the soft-start ramp to a value greater than
500μs to prevent inadvertent fault conditions due to excessive
inrush current.
14
Note that when Auto Compensation is enabled, the minimum
t ON_DELAY is 5ms.
Power-good (PG)
The ZL2101 provides a Power-good (PG) signal that indicates the
output voltage is within a specified tolerance of its target level
and no fault condition exists. By default, the PG pin will assert if
the output is within +15%/-10% of the target voltage. These
limits may be changed via the I 2 C/SMBus interface. See
Application Note AN2033 for details.
A PG delay period is the time from when all conditions for
asserting PG are met and when the PG pin is actually asserted.
This feature is commonly used instead of an external reset
controller to signal the power supply is at its target voltage prior
to enabling any powered circuitry. By default, the ZL2101 PG
delay is set to 1ms and may be changed using the I 2 C/SMBus
interface as described in AN2033.
FN7730.0
January 23, 2012
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