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| 型号： | ZL2101ALAF |
| 厂商： | Intersil |
| 文件页数： | 22/27页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 36QFN |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.54 V ~ 5.5 V |
| 输入电压： | 4.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
| 供应商设备封装： | 36-QFN（6x6） |
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ZL2101
timeout for the member's output voltage to turnoff in the event
that the reference output voltage does not achieve zero volts.
The member device(s) must have a minimum Time-Off Delay of
as shown in Equation 15.
Tracking Configured by Pin-Strap
Tracking is enabled with the CFG pin as shown in Table 16 on
as shown in Table 13 on page 23. Figure 22 shows the basic
tOFF DLY(MEM) ≥ tOFF DLY(REF) + tOFF FALL(REF) + 5ms
(EQ. 15)
schematic of pin-strap tracking.
It is assumed for a tracking group, that all of the ENABLE pins are
connected together and driven by a single logic source or PMBus
Broadcast Enable is used.
ENABLE
EN
ZL2101
SW
VOUT_R
L1
EN
ZL2101
VTRK
SW
VOUT_M
L2
The configuration settings for Figures 19 and 20 are shown
below in Figure 21. In each case the reference and member rise
times are set to the same value.
REFERENCE
CFG SS
MEMBER
CFG SS
R1
R3
R2
R4
Tracking ? Configuration ? Figure ? 20 ? (A)
Rail
Vout
Set
Time ? On
? Dly
Time ? On
Rise
Time ? Off
? Dly
Time ? Off
Fall
Mode
FIGURE 22. BASIC PIN-STRAP TRACKING CONFIGURATION
(Volts)
(ms)
(ms)
(ms)
( ? ms)
Reference
Member
1.8
0.9
15
5
5
5
5
15
5
5
Track ? Disabled
100% ? Vout ? Limited
Voltage Margining
Rail
Reference
Member
Vout ? Set
(Volts)
1.8
1.8
Tracking ? Configuration ? Figure ? 20 ? (B)
Time ? On Time ? On Time ? Off Time ? Off
? Dly Rise ? Dly Fall
(ms) (ms) (ms) ( ? ms)
15 5 5 5
5 5 15 5
Mode
Track ? Disabled
100% ? VTRK ? Limited
The ZL2101 offers a simple means to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. The MGN command is set by driving the
MGN pin or through the I 2 C/SMBus interface. The MGN pin is a
tri-level input that is continuously monitored and can be driven
Tracking ? Configuration ? Figure ? 21 ? (A)
directly by a processor I/O pin or other logic-level output.
Rail
Vout ? Set
(Volts)
Time ? On
? Dly
(ms)
Time ? On
Rise
(ms)
Time ? Off
? Dly
(ms)
Time ? Off
Fall
( ? ms)
Mode
The ZL2101’s output will be forced higher than its nominal set
point when the MGN command is set HIGH, and the output will
Reference 1.8 15 5 5 5 Track ? Disabled
Member 0.9 5 5 15 5 Track ? 50% ? Vout ? Limited
Tracking ? Configuration ? Figure ? 21 ? (B)
Time ? On Time ? On Time ? Off Time ? Off
Vout ? Set
Rail 0.8 ? Dly Rise ? Dly Fall Mode
(Volts)
(ms) (ms) (ms) ( ? ms)
Reference 1.8 15 5 5 5 Track ? Disabled
Member 1.8 5 5 15 5 Track ? 50% ? VTRK ? Limited
FIGURE 21. TRACKING CONFIGURATION FOR FIGURES 19 AND 20
22
be forced lower than its nominal set point when the MGN
command is set LOW. Default margin limits of V NOM ±5% are
pre-loaded in the factory, but the margin limits can be modified
through the I 2 C/SMBus interface to as high as V NOM + 10% or as
low as 0V, where V NOM is the nominal output voltage set point
determined by the VSET pin. A safety feature prevents the user
from configuring the output voltage to exceed V NOM + 10% under
any conditions.
The margin limits and the MGN command can both be set
individually through the I 2 C/SMBus interface. Additionally, the
transition rate between the nominal output voltage and either
margin limit can be configured through the I 2 C/SMBus interface.
Please refer to Application Note AN2033 for detailed instructions
on modifying the margining configurations.
FN7730.0
January 23, 2012
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