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| 型号： | ZL2101ALAF |
| 厂商： | Intersil |
| 文件页数： | 21/27页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 36QFN |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.54 V ~ 5.5 V |
| 输入电压： | 4.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
| 供应商设备封装： | 36-QFN（6x6） |
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ZL2101
Voltage Tracking
High performance systems place stringent demands on the order
in which the power supply voltages turn on. This is particularly
true when powering FPGAs, ASICs, and other advanced processor
devices that require multiple supply voltages to power a single
die. In most cases, the I/O interface operates at a higher voltage
than the core and therefore the core supply voltage must not
exceed the I/O supply voltage according to the manufacturers'
specifications. Voltage tracking protects these sensitive ICs by
limiting the differential voltage among multiple power supplies
during the power-up and power-down sequence. The ZL2101
integrates a lossless tracking scheme that allows its output to
2. Ratiometric. This mode configures the ZL2101 to ramp its
output voltage as a percentage of the voltage applied to the
VTRK pin. The default setting is 50%, but an external resistor
may be used to configure a different tracking ratio.
a. Track at 50% V OUT limited. Member rail tracks the reference
rail and stops when the member reaches 50% of the target
voltage, Figure 20 (A).
b. Track at 50% VTRK limited. Member rail tracks the reference
at the instantaneous voltage value applied to the VTRK pin
until the member rail reaches 50% of the reference rail
voltage, or if the member is configured to less than 50% of the
reference the member will achieve its configured target,
track a voltage that is applied to the VTRK pin with no additional
components required. Figure 18 shows a basic I 2 C/SMBus
tracking configuration. Please refer to Application Note AN2033
for more information on configuring tracking mode using PMBus
commands.
Figure 22 is an example of a basic pin-strap tracking
configuration. The VTRK pin is an analog input that, when
tracking mode is enabled, the voltage applied to the VTRK pin
Figure 20 (B).
TRACK @ 50% V OUT LIMITED
V REF = 1.8V
V MEM = 0.9V V REF
t ON_DLY
0
EN
A. TRACK @ 50% V
TRK LIMITED
t OFF_DLY
V MEM
V REF = 1.8V
V MEM = 0.9V
performs as a reference for the device's output voltage. The
ZL2101 offers two modes of tracking: coincident and ratiometric.
Figures 19 and 20 illustrate the output voltage waveform for the
two tracking modes.
0
V REF = 1.8V
V MEM = 0.9V V REF
t ON_DLY
EN
t OFF_DLY
V MEM
V REF = 1.8V
V MEM = 0.9V
SDA
SCL
B.
FIGURE 20. RATIOMETRIC TRACKING
SDA SCL
ZL2101
SW
REFERENCE
VOUT_R
L4
SDA SCL
ZL2101
VTRK SW
MEMBER
VOUT_M
L3
Tracking Overview
When the ZL2101 is configured to the voltage tracking mode, the
voltage applied to the VTRK pin acts as a reference for the
member device(s) output regulation. The soft-start values
FIGURE 18. BASIC I 2 C TRACKING CONFIGURATION
1. Coincident. This mode configures the ZL2101 to ramp its
output voltage at the same rate as the voltage applied to the
VTRK pin. Two options are available for this mode;
a. Track at 100% V OUT limited. Member rail tracks the reference
rail and stops when the member reaches its target voltage,
Figure 19 (A).
b. Track at 100% VTRK limited. Member rail tracks the
reference at the instantaneous voltage value applied to the
VTRK pin, Figure 19 (B).
(Rise/Fall times) are used to calculate the loop gain used during
the turn-on/turn-off ramps, therefore the minimum rise/fall time
has been constrained to 5ms to ensure accuracy. Tracking
accuracy can be improved by increasing the rise and fall times
beyond 5ms.
Tracking Groups
In a tracking group, the device configured to the highest voltage
within the group is defined as the reference device. The device(s)
that track the reference are called the member device(s). The
reference device will control the ramp delay and ramp rate of all
tracking devices and is not placed in the tracking mode.
0
TRACK @ 100% V OUT LIMITED
V REF > V MEM V REF
t ON_DLY
t OFF_DLY
V MEM
V REF = 1.8V
V MEM = 0.9V
The reference device is configured to the highest output voltage
for the group and all other device(s) output voltages are meant to
track and never exceed the reference device output voltage.
The reference device must be configured to have a minimum
EN
Time-On Delay and Time-On Rise as shown in Equation 14.
A. TRACK @ 100% V
TRK LIMITED
tON DLY(REF) ≥ tON DLY(MEM) + tON RISE(REF) + 5ms ≥ tON DLY(MEM) + 10ms
0
V REF = V MEM V REF
t ON_DLY
t OFF_DLY
V MEM
V REF = 1.8V
V MEM = 1.8V
(EQ. 14)
This delay allows the member device(s) to prepare their control
EN
loops for tracking following the assertion of ENABLE.
B.
FIGURE 19. COINCIDENT TRACKING
21
The member device Time-Off Delay has been redefined to
describe the time that the VTRK pin will follow the reference
voltage after enable is de-asserted. The delay setting sets the
FN7730.0
January 23, 2012
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