参数资料
型号: ZL2101ALAF
厂商: Intersil
文件页数: 2/27页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 6A 36QFN
标准包装: 50
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.54 V ~ 5.5 V
输入电压: 4.5 V ~ 14 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 1MHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-VFQFN 裸露焊盘
包装: 托盘
供应商设备封装: 36-QFN(6x6)
ZL2101
Typical Application Circuit
The following application circuit represents a typical implementation of the ZL2101. For PMBus operation, it is recommended to tie the
enable pin (EN) to SGND.
C RA
4.7 μF
F.B.
?
V IN
DDC Bus
?
C 25
10 μF
C R
4.7μF
C DD
2.2 μF
12V
ENABLE
C IN
100 μF
PGOOD
1 PG
2 DGND
3 SYNC
VDDP 27
BST 26
SW 25
C B
47nF
ZL2106
I 2 C/
SMBus ??
4 VSET
5 SA
6 SCL
7 SDA
8 SALRT
ZL2101
SW 24
SW 23
SW 22
SW 21
SW 20
L OUT
2.2μH
C OUT
V OUT
3.3V
9 FC
PGND 19
150 μF
Ferrite bead is optional for input noise suppression.
The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
The I C/SMBus pull -up resistance will vary based on the capacitive loading of the bus, including the number of devices
Notes:
?
?
connected. The 10 k Ω default value, assuming a maximum of 100 pF per device, provides the necessary 1 μs pull-up rise
time. Please refer to the Digital-DC Bus section for more details.
?? 2
connected. Please refer to the I 2 C/SMBus specifications for more details.
FIGURE 2. 12V TO 3.3V/6A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP)
Block Diagram
V IN
EN
2.5V
LDO
5V
LDO
7V
LDO
BST
PG
MGN
VSET
CFG
SS
VTRK
Power
Mgmt
PWM
Control
&
Drivers
SW
V OUT
DDC
SA
DDC Bus
SMBus
NVM
VSEN
FIGURE 3. BLOCK DIAGRAM
2
FN7730.0
January 23, 2012
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