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参数资料
| 型号： | ZL50418GKG2 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553 |
| 文件页数： | 109/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418GKG2 |
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ZL50418
Data Sheet
57
Zarlink Semiconductor Inc.
7.2
Frame Engine Details
This section briefly describes the functions of each of the modules of the ZL50418 frame engine.
7.2.1
FCB Manager
The FCB manager allocates FCB handles to incoming frames and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits. In addition, the FCB manager is
responsible for buffer aging and for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be
enabled or disabled by the bootstrap pin and the aging time is defined in register FCBAT.
7.2.2
Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
7.2.3
RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
7.2.4
TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation and using this
information makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the
TxQ manager requests that the FCB manager link the unicast frame’s FCB to the correct per-port-per-class TxQ. If
multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger
source port flow control for the incoming frame’s source if that port is flow control enabled. Second, the TxQ
manager handles transmission scheduling; it schedules transmission among the queues representing different
classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to
the correct port control module.
7.2.5
Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes
start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control
module requests that the buffer be released.
7.2.6
TxDMA
The TxDMA multiplexes data and address from port control and arbitrates among buffer release requests from the
port control modules.
8.0
Quality of Service and Flow Control
8.1
Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general,
the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also
assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager
knows his applications, such as voice, file transfer, or web browsing and their relative importance. The manager
can then subdivide the applications into classes and set up a service contract with each. The contract may consist
of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to
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