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参数资料
| 型号： | ZL50418GKG2 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553 |
| 文件页数： | 115/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418GKG2 |
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ZL50418
Data Sheet
62
Zarlink Semiconductor Inc.
to be 12 kilobytes. The number of bytes is measured in 8-byte increments, so the 16-bit field “Maximum burst size”
is set to 12000/8, or 1500.
8.8
WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behavior of the WRED logic.
Table 10 - WRED Drop Thresholds
Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of
N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals
P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined
high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can
be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are
dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds
for each priority queue. They can be programmed by the QOS control register (refer to the register group 5).
See Programming QoS Registers Application Note, ZLAN-05, for more information.
8.9
Buffer Management
Because the number of FDB slots is a scarce resource and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the ZL50418. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool as shown in Figure 14 on page 63.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the ZL50418, its destination port and class are as yet unknown, and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per
class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100M ports, a frame
is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only four
transmission scheduling queues for 10/100 M ports, but as far as buffer usage is concerned there are still eight
distinguishable classes.
Another segment of the FDB reserves space for each of the ports — 18 ports for Ethernet and one CPU port (port
number 24). Two parameters can be set, one for the source port reservation for 10/100 M ports and CPU port, and
one for the source port reservation for Gigabit ports. These reserved regions make sure that no well-behaved
source port can be blocked by another misbehaving source port.
In KB (kilobytes)
P3
P2
P1
High Drop
Low Drop
Level 1
N
≥ 120
P3
≥ AKB
P2
≥ BKB
P1
≥ CKB
X%
0%
Level 2
N
≥ 140
Y%
Z%
Level 3
N
≥ 160
100%
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