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参数资料
型号： ZL50418GKG2
厂商： CONEXANT SYSTEMS
元件分类： 网络接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA553
封装： 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
文件页数： 23/155页
文件大小： 1928K
代理商： ZL50418GKG2
ZL50418
Data Sheet
119
Zarlink Semiconductor Inc.
User Defined Logical Ports and Well Known Ports
The ZL50418 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well
Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are:
23
512
6000
443
111
22555
22
554
Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_Enable
can individually turn on/off each Well Known Port if desired.
Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select
specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7
registers. Two registers are required to be programmed for the logical port number. The respective priority can be
programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper
limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than
the upper limit and more than the lower limit will use the priority specified in RPRIORITY.
12.3.6.40
USER_PORT0~7)_L/H – USER DEFINE LOGICAL PORT (0~7)
USER_PORT0_L/H - I2C Address h0D6 + 0DE; CPU Address 580(Low) + 581(high)
USER_PORT1_L/H - I2C Address h0D7 + 0DF; CPU Address 582 + 583
USER_PORT2_L/H - I2C Address h0D8 + 0E0; CPU Address 584 + 585
USER_PORT3_L/H - I2C Address h0D9 + 0E1; CPU Address 586 + 587
USER_PORT4_L/H - I2C Address h0DA + 0E2; CPU Address 588 + 589
USER_PORT5_L/H - I2C Address h0DB + 0E3; CPU Address 58A + 58B
USER_PORT6_L/H - I2C Address h0DC + 0E4; CPU Address 58C + 58D
USER_PORT7_L/H - I2C Address h0DD + 0E5; CPU Address 58E + 58F
Accessed by CPU, serial interface and I2C (R/W)
Bits [3:0]:
Corresponds to the best effort frame drop percentage B%, when shared pool
is all in use and destination port best effort queue reaches UCC. Granularity
6.25%.
See Programming QoS Registers application note for more information
70
TCP/UDP Logic Port Low
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