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参数资料
| 型号： | 5962-9205805QXA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 60 MHz, OTHER DSP, CPGA141 |
| 封装： | STAGGERED, CERAMIC, PGA-141 |
| 文件页数： | 21/54页 |
| 文件大小： | 1033K |
| 代理商： | 5962-9205805QXA |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
timing for XFx changing from input to output mode (see Figure 22)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
37
td(H3H-XFIO)
Delay time, H3 high to XFx switching from input to output
17
16
ns
Execution of
Load of IOF
37
H3
H1
I / OxFx
Bit
(see Note A)
XFx Pin
NOTE A: I / OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 22. Timing for Change of XFx From Input to Output Mode
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 23 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states
and therefore results in slow external accesses until these registers are initialized.
HOLD is an asynchronous input and can be asserted during reset.
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