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| 型号： | 5962-9205805QXA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 60 MHz, OTHER DSP, CPGA141 |
| 封装： | STAGGERED, CERAMIC, PGA-141 |
| 文件页数： | 7/54页 |
| 文件大小： | 1033K |
| 代理商： | 5962-9205805QXA |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLoad
IOL
CT
IOH
Output
Under
Test
Where:
IOL
= 2 mA (all outputs)
IOH
= 300
A (all outputs)
VLOAD = Selected to emulate 50- termination (typical value = 1.54 V).
CT
= 80-pF typical load-circuit capacitance
Figure 4. SMJ320C31 Test Load Circuit
signal transition levels for ’C31 (see Figure 5 and Figure 6)
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
D For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
D For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
0.6 V
1 V
2 V
2.4 V
Figure 5. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2.1 V and the level at which the input is said to be low is 0.8 V.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V and the level at which the input is said to be high is 2.1 V.
0.8 V
2.1 V
Figure 6. TTL-Level Inputs
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相关代理商/技术参数 |
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|---|---|
| 5962-9205805QYA | 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 60MHZ 30MIPS 132CFPAK - Rail/Tube |
| 596292062012MYC | 制造商:ALTERA 功能描述:EPM5192GM883B |
| 5962-92062012MYC | 制造商:ALTERA 功能描述:EPM5192GM883B |
| 5962-9206201MYC | 制造商:Cypress Semiconductor 功能描述:CPLD 192 Macro Cells 0.8um (CMOS) Technology 5V 84-Pin Windowed PGA |
| 5962-9206202MYC | 制造商:e2v Aerospace & Defense 功能描述:CPLD, UV ERASABLE, 192-MACROCELL, 30 NS PROP. DELAY TIME |
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