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参数资料
| 型号： | 5962-9205805QXA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 60 MHz, OTHER DSP, CPGA141 |
| 封装： | STAGGERED, CERAMIC, PGA-141 |
| 文件页数： | 25/54页 |
| 文件大小： | 1033K |
| 代理商： | 5962-9205805QXA |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
interrupt response timing
The following table defines the timing parameters for the INT signals.
timing for INT3INT0 response (see Figure 24)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
50
tsu(INT-H1L)
Setup time, INT3INT0 before H1 low
13
15
11
8
ns
51
tw(INT)
Pulse duration, interrupt to ensure
only one interrupt
P
2P*
P
2P*
P
2P*
P
2P*
ns
P = tc(H)
* This parameter is not production tested.
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SMJ320C3x interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D A minimum of one H1 falling edge
D No more than two H1 falling edges
The SMJ320C3x can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 24 occurs; otherwise, an additional delay
of one clock cycle is possible.
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