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参数资料
| 型号： | 70T3399S133DD |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件页数： | 18/28页 |
| 文件大小： | 429K |
| 代理商： | 70T3399S133DD |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
25
JTAG AC Electrical
Characteristics (1,2,3,4)
JTAG Timing Specifications
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
TCK
Device Inputs(1)/
TDI/TMS
Device Outputs(2)/
TDO
TRST
tJCD
tJDC
tJRST
tJS
tJH
tJCYC
tJRSR
tJF
tJCL
tJR
tJCH
5652 drw 23
,
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
70T3339/19/99
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
3(1)
ns
tJF
JTAG Clock Fall Time
____
3(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
5652 tbl 15
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