参数资料
型号: 70T3399S133DD
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: SRAM
英文描述: 128K X 18 DUAL-PORT SRAM, 15 ns, PQFP144
封装: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件页数: 8/28页
文件大小: 429K
代理商: 70T3399S133DD
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
16
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
5652 drw 11
Qn
Qn + 3
DATAOUT
CE1
UB, LB
tCD2
tCKHZ
tCKLZ
tCD2
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
tCH2
tCL2
tCYC2
READ
NOP
READ
tSD tHD
(3)
(1)
tSW tHW
WRITE
(4)
,
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATAIN
Dn + 3
Dn + 2
CE0
CLK
5652 drw 12
DATAOUT
Qn
Qn + 4
CE1
UB, LB
OE
tCH2
tCL2
tCYC2
tCKLZ
tCD2
tOHZ
tCD2
tSD
tHD
READ
WRITE
READ
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
(3)
(1)
tSW tHW
(4)
,
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
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