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参数资料
| 型号： | 70T3399S133DD |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件页数： | 5/28页 |
| 文件大小： | 429K |
| 代理商： | 70T3399S133DD |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
13
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
An
An + 1
An + 2
An + 3
tCYC2
tCH2
tCL2
R/W
ADDRESS
CE0
CLK
CE1
UB, LB
(3)
DATAOUT
OE
tCD2
tCKLZ
Qn
Qn + 1
Qn + 2
tOHZ
tOLZ
tOE
5652 drw 05
(1)
tSC
tHC
tSB
tHB
tSW
tHW
tSA
tHA
tDC
tSC
tHC
tSB
tHB
(4)
(1 Latency)
(5)
,
An
An + 1
An + 2
An + 3
tCYC1
tCH1
tCL1
R/W
ADDRESS
DATAOUT
CE0
CLK
OE
tSC
tHC
tCD1
tCKLZ
Qn
Qn + 1
Qn + 2
tOHZ
tOLZ
tOE
tCKHZ
5652 drw 06
(5)
(1)
CE1
UB, LB
(3)
tSB
tHB
tSW
tHW
tSA
tHA
tDC
(4)
tSC
tHC
tSB
tHB
,
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