- 您现在的位置：买卖IC网 > PDF目录68811 > 71M6531D-IM/F (TERIDIAN SEMICONDUCTOR CORP) 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 PDF资料下载
参数资料
| 型号： | 71M6531D-IM/F |
| 厂商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封装： | LEAD FREE, QFN-68 |
| 文件页数： | 54/120页 |
| 文件大小： | 2477K |
| 代理商： | 71M6531D-IM/F |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页当前第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
39
The simplest flash write procedure disables the CE during the write operation and interpolates the metering
measurements. However, this results in the loss of at least one second of data, because the CE has to
resynchronize with the mains voltage.
There is a brief guaranteed interval (typically 1/32768 s) between CE executions which occurs 2520 times
per second. The start of the interval can be detected with the CE_BUSY interrupt which occurs on the
falling edge of CE_BUSY (an internal signal measurable from TMUXOUT). However, this guaranteed idle
time (30.5 s) is too short to write a byte which takes 42 s or to erase a page of flash memory which
takes at least 20 ms. Some CE code has substantially longer idle times, but in those cases, firmware
interrupt latencies can easily consume the available write time. If a flash write fails in this scheme, the
failure can be detected with the FWCOL0 or FWCOL1 interrupt and the write can be retried.
It is practical to pre-erase pages, disable interrupts and poll the CE_BUSY interrupt flag, IRCON[2]. This
method avoids problems with interrupt latency, but can still result in a write failure if the CE code takes to
much time. As mentioned above, polling FWCOL0 and FWCOL1 can detect write failures. However, the
speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupts.
As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM interfaces
are included in the device.
The original state of a flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Updating Individual Bytes in Flash Memory
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
Flash Erase Procedures
The mass erase sequence is:
1.
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
2.
Write pattern 0xAA to FLSH_ERASE (SFR 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1.
Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:1]).
2.
Write pattern 0x55 to FLSH_ERASE (SFR 0x94).
The program memory of the 71M6531 consists of a fixed lower bank of 32 KB addressable at 0x0000 to
0x7FFF plus an upper bank area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is
banked using the I/O RAM FL_BANK register as follows:
Bank-Switching:
The 71M6531D provides 4 banks of 32 KB each selected by FL_BANK[1:0]. Note that when
FL_BANK[1:0] = 00, the upper bank is the same as the lower bank.
The 71M6531F and 71M6532D/F provide 8 banks of 32 KB each selected by FL_BANK[2:0].
Table 38 illustrates the bank switching mechanism.
相关PDF资料 |
PDF描述 |
|---|---|
| 71M6532F-IGTR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 71M6534-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP120 |
| 71M6534H-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP120 |
| 71M6533H-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6534-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP120 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6531D-IMR/F | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531D-IMR/F1 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531D-IMR/F2 | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Energy Meter IC |
| 71M6531F-DB | 功能描述:开发板和工具包 - 8051 71M6531F Demo Brd RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
发布紧急采购，3分钟左右您将得到回复。