参数资料
| 型号： | 71M6531F-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 32/121页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 71M6531F |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是 |
| 已用 IC / 零件： | 71M6531 |
| 主要属性： | 单相功率表 |
| 已供物品： | 2 个板，线缆，CD，电源 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
IRCON[1]
IRCON[0]
IEX2
–
1 = External interrupt 2 occurred and has not been cleared.
Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when
the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in
other parts of the 71M6531D/F or 71M6532D/F, for example the CE, DIO, RTC or EEPROM interface.
The external interrupts are connected as described in Table 30 . The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8) . Interrupts 2 and 3 should be
programmed for falling sensitivity ( I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts
4 through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5 and
Table 30: External MPU Interrupts
External
Interrupt
0
1
2
3
4
5
6
Connection
Digital I/O High Priority
Digital I/O Low Priority
FWCOL0, FWCOL1, SPI
CE_BUSY
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
XFER_BUSY, RTC_1SEC or WD_NROVF
Polarity
see Section 1.5.7
see Section 1.5.7
falling
falling
rising
falling
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section
1.5.7 Digital I/O for more information.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the Flash Write description
in the Flash Memory section for more detail.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler.
XFER_BUSY, RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their
own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 31 ).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other
flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided . The hardware implements bit operations as a
byte-wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Name Location
Interrupt Flag
Name Location
Interrupt Description
EX0
EX1
EX2
EX3
SFR A8[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
IE0
IE1
IEX2
IEX3
SFR 88[1]
SFR 88[3]
SFR C0[1]
SFR C0[2]
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
32
Rev 2
相关PDF资料 |
PDF描述 |
|---|---|
| 71M6533-DB | BOARD DEMO 71M6533 |
| 71M6534H-DB | BOARD DEMO 71M6534H |
| 71M6541F-DB | DEMO BOARD 71M6541F |
| 71M6543F-DB-CT | DEMO BOARD 71M6543F-DB-CT |
| 72-CNV-5 | CONVERTER RS-232 TO RS-422 5V |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6531F-IM/F | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F-IM/F3 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F-IM/F4 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F-IM/FR4 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6531F-IMR/F | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。