参数资料
型号: 71M6531F-DB
厂商: Maxim Integrated Products
文件页数: 84/121页
文件大小: 0K
描述: BOARD DEMO 71M6531F
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: 71M6531
主要属性: 单相功率表
已供物品: 2 个板,线缆,CD,电源
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Name
MUX_ALT
MUX_DIV[3:0]
MUX_SYNC_E
Location
2005[2]
209D[3:0]
2020[7]
Reset
0
0
0
Wake
0
0
0
Dir
R/W
R/W
R/W
Description
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E[1:0] is 00, MUX_ALT is automatically asserted once per sumcycle, when
XFER_BUSY falls.
The number of states in the input multiplexer.
When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
Selects the modulation duty cycle for OPT_TX.
OPT_FDC[1:0]
Function
OPT_FDC[1:0]
2007[1:0]
0
0
R/W
00
01
50% Low
25% Low
10
11
12.5% Low
6.25% Low
OPT_RXDIS
OPT_RXINV
2008[5]
2008[4]
0
0
0
0
R/W
R/W
Configures OPT_RX to an analog input to the optical UART comparator or as a digital
input/output, DIO1: 0 = OPT_RX, 1 = DIO1.
Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
OPT_TXE[1:0]
Function
OPT_TXE[1:0]
2007[7:6]
00
00
R/W
00
01
OPT_TX
DIO2
10
11
WPULSE
RPULSE
OPT_TXINV
OPT_TXMOD
PLL_OK
PLS_MAXWIDTH
[7:0]
PLS_INTERVAL
[7:0]
2008[0]
2008[1]
2003[6]
2080[7:0]
2081[7:0]
0
0
0
FF
0
0
0
0
FF
0
R/W
R/W
R
R/W
R/W
Inverts OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inversion
caused by OPT_TXINV .
Indicates that system power is present and the clock generation PLL is settled.
Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*T I . Where T I is PLS_INTERVAL .
If PLS_INTERVAL = 0, T I is the sample time (397 μs). If set to 255, pulse width control
is disabled and pulses are output with a 50% duty cycle.
For PULSE_W and PULSE_V only: If the FIFO is used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the
CE issues them.
84
Rev 2
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